Lines Matching refs:nitrox_write_csr
31 nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value); in emu_enable_cores()
32 nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value); in emu_enable_cores()
59 nitrox_write_csr(ndev, offset, emu_wd_int.value); in nitrox_config_emu_unit()
61 nitrox_write_csr(ndev, offset, emu_ge_int.value); in nitrox_config_emu_unit()
76 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in reset_pkt_input_ring()
90 nitrox_write_csr(ndev, offset, pkt_in_cnts.value); in reset_pkt_input_ring()
105 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in enable_pkt_input_ring()
138 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_pkt_input_rings()
144 nitrox_write_csr(ndev, offset, pkt_in_rsize.value); in nitrox_config_pkt_input_rings()
148 nitrox_write_csr(ndev, offset, 0xffffffff); in nitrox_config_pkt_input_rings()
154 nitrox_write_csr(ndev, offset, pkt_in_dbell.value); in nitrox_config_pkt_input_rings()
172 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in reset_pkt_solicit_port()
187 nitrox_write_csr(ndev, offset, pkt_slc_cnts.value); in reset_pkt_solicit_port()
207 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in enable_pkt_solicit_port()
230 nitrox_write_csr(ndev, offset, pkt_slc_int.value); in config_pkt_solicit_port()
261 nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value); in enable_nps_core_interrupts()
269 nitrox_write_csr(ndev, NPS_CORE_CONTROL, 1ULL); in nitrox_config_nps_core_unit()
275 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value); in nitrox_config_nps_core_unit()
290 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
291 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
292 nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
294 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
295 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
296 nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL)); in enable_nps_pkt_interrupts()
321 nitrox_write_csr(ndev, offset, aqmq_en_reg.value); in reset_aqm_ring()
336 nitrox_write_csr(ndev, offset, cmp_cnt.value); in reset_aqm_ring()
348 nitrox_write_csr(ndev, offset, aqmq_en_reg.value); in enable_aqm_ring()
370 nitrox_write_csr(ndev, offset, drbl.value); in nitrox_config_aqm_rings()
376 nitrox_write_csr(ndev, offset, 0ULL); in nitrox_config_aqm_rings()
380 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_aqm_rings()
386 nitrox_write_csr(ndev, offset, qsize.value); in nitrox_config_aqm_rings()
392 nitrox_write_csr(ndev, offset, cmp_thr.value); in nitrox_config_aqm_rings()
402 nitrox_write_csr(ndev, AQM_DBELL_OVF_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
403 nitrox_write_csr(ndev, AQM_DBELL_OVF_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
404 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
405 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
406 nitrox_write_csr(ndev, AQM_EXEC_NA_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
407 nitrox_write_csr(ndev, AQM_EXEC_NA_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
408 nitrox_write_csr(ndev, AQM_EXEC_ERR_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
409 nitrox_write_csr(ndev, AQM_EXEC_ERR_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
429 nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value); in nitrox_config_pom_unit()
433 nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i)); in nitrox_config_pom_unit()
449 nitrox_write_csr(ndev, offset, efl_rnm_ctl.value); in nitrox_config_rand_unit()
466 nitrox_write_csr(ndev, offset, efl_core_int.value); in nitrox_config_efl_unit()
469 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
471 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
487 nitrox_write_csr(ndev, offset, bmi_ctl.value); in nitrox_config_bmi_unit()
495 nitrox_write_csr(ndev, offset, bmi_int_ena.value); in nitrox_config_bmi_unit()
507 nitrox_write_csr(ndev, offset, bmo_ctl2.value); in nitrox_config_bmo_unit()
521 nitrox_write_csr(ndev, offset, lbc_ctl.value); in invalidate_lbc()
546 nitrox_write_csr(ndev, offset, lbc_int_ena.value); in nitrox_config_lbc_unit()
549 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
551 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
554 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
556 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
566 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, vfcfg.value); in config_nps_core_vfcfg_mode()
660 nitrox_write_csr(ndev, reg_addr, value); in enable_pf2vf_mbox_interrupts()
664 nitrox_write_csr(ndev, reg_addr, value); in enable_pf2vf_mbox_interrupts()
674 nitrox_write_csr(ndev, reg_addr, value); in disable_pf2vf_mbox_interrupts()
678 nitrox_write_csr(ndev, reg_addr, value); in disable_pf2vf_mbox_interrupts()