Lines Matching refs:ndev
15 static void emu_enable_cores(struct nitrox_device *ndev) in emu_enable_cores() argument
31 nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value); in emu_enable_cores()
32 nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value); in emu_enable_cores()
40 void nitrox_config_emu_unit(struct nitrox_device *ndev) in nitrox_config_emu_unit() argument
48 emu_enable_cores(ndev); in nitrox_config_emu_unit()
59 nitrox_write_csr(ndev, offset, emu_wd_int.value); in nitrox_config_emu_unit()
61 nitrox_write_csr(ndev, offset, emu_ge_int.value); in nitrox_config_emu_unit()
65 static void reset_pkt_input_ring(struct nitrox_device *ndev, int ring) in reset_pkt_input_ring() argument
74 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
76 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in reset_pkt_input_ring()
81 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
89 pkt_in_cnts.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
90 nitrox_write_csr(ndev, offset, pkt_in_cnts.value); in reset_pkt_input_ring()
94 void enable_pkt_input_ring(struct nitrox_device *ndev, int ring) in enable_pkt_input_ring() argument
102 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_input_ring()
105 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in enable_pkt_input_ring()
109 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_input_ring()
120 void nitrox_config_pkt_input_rings(struct nitrox_device *ndev) in nitrox_config_pkt_input_rings() argument
124 for (i = 0; i < ndev->nr_queues; i++) { in nitrox_config_pkt_input_rings()
125 struct nitrox_cmdq *cmdq = &ndev->pkt_inq[i]; in nitrox_config_pkt_input_rings()
130 reset_pkt_input_ring(ndev, i); in nitrox_config_pkt_input_rings()
138 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_pkt_input_rings()
143 pkt_in_rsize.s.rsize = ndev->qlen; in nitrox_config_pkt_input_rings()
144 nitrox_write_csr(ndev, offset, pkt_in_rsize.value); in nitrox_config_pkt_input_rings()
148 nitrox_write_csr(ndev, offset, 0xffffffff); in nitrox_config_pkt_input_rings()
154 nitrox_write_csr(ndev, offset, pkt_in_dbell.value); in nitrox_config_pkt_input_rings()
157 enable_pkt_input_ring(ndev, i); in nitrox_config_pkt_input_rings()
161 static void reset_pkt_solicit_port(struct nitrox_device *ndev, int port) in reset_pkt_solicit_port() argument
170 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
172 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in reset_pkt_solicit_port()
178 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
186 pkt_slc_cnts.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
187 nitrox_write_csr(ndev, offset, pkt_slc_cnts.value); in reset_pkt_solicit_port()
191 void enable_pkt_solicit_port(struct nitrox_device *ndev, int port) in enable_pkt_solicit_port() argument
207 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in enable_pkt_solicit_port()
211 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_solicit_port()
218 static void config_pkt_solicit_port(struct nitrox_device *ndev, int port) in config_pkt_solicit_port() argument
223 reset_pkt_solicit_port(ndev, port); in config_pkt_solicit_port()
230 nitrox_write_csr(ndev, offset, pkt_slc_int.value); in config_pkt_solicit_port()
233 enable_pkt_solicit_port(ndev, port); in config_pkt_solicit_port()
236 void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev) in nitrox_config_pkt_solicit_ports() argument
240 for (i = 0; i < ndev->nr_queues; i++) in nitrox_config_pkt_solicit_ports()
241 config_pkt_solicit_port(ndev, i); in nitrox_config_pkt_solicit_ports()
250 static void enable_nps_core_interrupts(struct nitrox_device *ndev) in enable_nps_core_interrupts() argument
261 nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value); in enable_nps_core_interrupts()
264 void nitrox_config_nps_core_unit(struct nitrox_device *ndev) in nitrox_config_nps_core_unit() argument
269 nitrox_write_csr(ndev, NPS_CORE_CONTROL, 1ULL); in nitrox_config_nps_core_unit()
275 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value); in nitrox_config_nps_core_unit()
278 enable_nps_core_interrupts(ndev); in nitrox_config_nps_core_unit()
287 static void enable_nps_pkt_interrupts(struct nitrox_device *ndev) in enable_nps_pkt_interrupts() argument
290 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
291 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
292 nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
294 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
295 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
296 nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL)); in enable_nps_pkt_interrupts()
299 void nitrox_config_nps_pkt_unit(struct nitrox_device *ndev) in nitrox_config_nps_pkt_unit() argument
302 nitrox_config_pkt_input_rings(ndev); in nitrox_config_nps_pkt_unit()
303 nitrox_config_pkt_solicit_ports(ndev); in nitrox_config_nps_pkt_unit()
306 enable_nps_pkt_interrupts(ndev); in nitrox_config_nps_pkt_unit()
309 static void reset_aqm_ring(struct nitrox_device *ndev, int ring) in reset_aqm_ring() argument
321 nitrox_write_csr(ndev, offset, aqmq_en_reg.value); in reset_aqm_ring()
327 activity_stat.value = nitrox_read_csr(ndev, offset); in reset_aqm_ring()
335 cmp_cnt.value = nitrox_read_csr(ndev, offset); in reset_aqm_ring()
336 nitrox_write_csr(ndev, offset, cmp_cnt.value); in reset_aqm_ring()
340 void enable_aqm_ring(struct nitrox_device *ndev, int ring) in enable_aqm_ring() argument
348 nitrox_write_csr(ndev, offset, aqmq_en_reg.value); in enable_aqm_ring()
352 void nitrox_config_aqm_rings(struct nitrox_device *ndev) in nitrox_config_aqm_rings() argument
356 for (ring = 0; ring < ndev->nr_queues; ring++) { in nitrox_config_aqm_rings()
357 struct nitrox_cmdq *cmdq = ndev->aqmq[ring]; in nitrox_config_aqm_rings()
364 reset_aqm_ring(ndev, ring); in nitrox_config_aqm_rings()
370 nitrox_write_csr(ndev, offset, drbl.value); in nitrox_config_aqm_rings()
376 nitrox_write_csr(ndev, offset, 0ULL); in nitrox_config_aqm_rings()
380 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_aqm_rings()
385 qsize.host_queue_size = ndev->qlen; in nitrox_config_aqm_rings()
386 nitrox_write_csr(ndev, offset, qsize.value); in nitrox_config_aqm_rings()
392 nitrox_write_csr(ndev, offset, cmp_thr.value); in nitrox_config_aqm_rings()
395 enable_aqm_ring(ndev, ring); in nitrox_config_aqm_rings()
399 static void enable_aqm_interrupts(struct nitrox_device *ndev) in enable_aqm_interrupts() argument
402 nitrox_write_csr(ndev, AQM_DBELL_OVF_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
403 nitrox_write_csr(ndev, AQM_DBELL_OVF_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
404 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
405 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
406 nitrox_write_csr(ndev, AQM_EXEC_NA_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
407 nitrox_write_csr(ndev, AQM_EXEC_NA_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
408 nitrox_write_csr(ndev, AQM_EXEC_ERR_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
409 nitrox_write_csr(ndev, AQM_EXEC_ERR_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
412 void nitrox_config_aqm_unit(struct nitrox_device *ndev) in nitrox_config_aqm_unit() argument
415 nitrox_config_aqm_rings(ndev); in nitrox_config_aqm_unit()
418 enable_aqm_interrupts(ndev); in nitrox_config_aqm_unit()
421 void nitrox_config_pom_unit(struct nitrox_device *ndev) in nitrox_config_pom_unit() argument
429 nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value); in nitrox_config_pom_unit()
432 for (i = 0; i < ndev->hw.se_cores; i++) in nitrox_config_pom_unit()
433 nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i)); in nitrox_config_pom_unit()
440 void nitrox_config_rand_unit(struct nitrox_device *ndev) in nitrox_config_rand_unit() argument
446 efl_rnm_ctl.value = nitrox_read_csr(ndev, offset); in nitrox_config_rand_unit()
449 nitrox_write_csr(ndev, offset, efl_rnm_ctl.value); in nitrox_config_rand_unit()
452 void nitrox_config_efl_unit(struct nitrox_device *ndev) in nitrox_config_efl_unit() argument
466 nitrox_write_csr(ndev, offset, efl_core_int.value); in nitrox_config_efl_unit()
469 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
471 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
475 void nitrox_config_bmi_unit(struct nitrox_device *ndev) in nitrox_config_bmi_unit() argument
483 bmi_ctl.value = nitrox_read_csr(ndev, offset); in nitrox_config_bmi_unit()
487 nitrox_write_csr(ndev, offset, bmi_ctl.value); in nitrox_config_bmi_unit()
495 nitrox_write_csr(ndev, offset, bmi_int_ena.value); in nitrox_config_bmi_unit()
498 void nitrox_config_bmo_unit(struct nitrox_device *ndev) in nitrox_config_bmo_unit() argument
505 bmo_ctl2.value = nitrox_read_csr(ndev, offset); in nitrox_config_bmo_unit()
507 nitrox_write_csr(ndev, offset, bmo_ctl2.value); in nitrox_config_bmo_unit()
510 void invalidate_lbc(struct nitrox_device *ndev) in invalidate_lbc() argument
519 lbc_ctl.value = nitrox_read_csr(ndev, offset); in invalidate_lbc()
521 nitrox_write_csr(ndev, offset, lbc_ctl.value); in invalidate_lbc()
525 lbc_stat.value = nitrox_read_csr(ndev, offset); in invalidate_lbc()
532 void nitrox_config_lbc_unit(struct nitrox_device *ndev) in nitrox_config_lbc_unit() argument
537 invalidate_lbc(ndev); in nitrox_config_lbc_unit()
546 nitrox_write_csr(ndev, offset, lbc_int_ena.value); in nitrox_config_lbc_unit()
549 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
551 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
554 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
556 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
559 void config_nps_core_vfcfg_mode(struct nitrox_device *ndev, enum vf_mode mode) in config_nps_core_vfcfg_mode() argument
563 vfcfg.value = nitrox_read_csr(ndev, NPS_CORE_GBL_VFCFG); in config_nps_core_vfcfg_mode()
566 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, vfcfg.value); in config_nps_core_vfcfg_mode()
608 void nitrox_get_hwinfo(struct nitrox_device *ndev) in nitrox_get_hwinfo() argument
619 rst_boot.value = nitrox_read_csr(ndev, offset); in nitrox_get_hwinfo()
620 ndev->hw.freq = (rst_boot.pnr_mul + 3) * PLL_REF_CLK; in nitrox_get_hwinfo()
624 emu_fuse.value = nitrox_read_csr(ndev, offset); in nitrox_get_hwinfo()
627 ndev->hw.ae_cores += AE_CORES_PER_CLUSTER - dead_cores; in nitrox_get_hwinfo()
629 ndev->hw.se_cores += SE_CORES_PER_CLUSTER - dead_cores; in nitrox_get_hwinfo()
634 fus_dat1.value = nitrox_read_csr(ndev, offset); in nitrox_get_hwinfo()
637 ndev->hw.zip_cores = ZIP_MAX_CORES - dead_cores; in nitrox_get_hwinfo()
644 get_core_option(ndev->hw.se_cores, ndev->hw.ae_cores), in nitrox_get_hwinfo()
645 ndev->hw.freq, in nitrox_get_hwinfo()
646 get_feature_option(ndev->hw.zip_cores, ndev->hw.freq), in nitrox_get_hwinfo()
647 ndev->hw.revision_id); in nitrox_get_hwinfo()
650 strncpy(ndev->hw.partname, name, sizeof(ndev->hw.partname)); in nitrox_get_hwinfo()
653 void enable_pf2vf_mbox_interrupts(struct nitrox_device *ndev) in enable_pf2vf_mbox_interrupts() argument
660 nitrox_write_csr(ndev, reg_addr, value); in enable_pf2vf_mbox_interrupts()
664 nitrox_write_csr(ndev, reg_addr, value); in enable_pf2vf_mbox_interrupts()
667 void disable_pf2vf_mbox_interrupts(struct nitrox_device *ndev) in disable_pf2vf_mbox_interrupts() argument
674 nitrox_write_csr(ndev, reg_addr, value); in disable_pf2vf_mbox_interrupts()
678 nitrox_write_csr(ndev, reg_addr, value); in disable_pf2vf_mbox_interrupts()