22 	emu_ae.value = 0;  in emu_enable_cores()
26 	emu_se.value = 0;  in emu_enable_cores()
31 		nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value);  in emu_enable_cores()
32 		nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value);  in emu_enable_cores()
51 	emu_ge_int.value = 0;  in nitrox_config_emu_unit()
54 	emu_wd_int.value = 0;  in nitrox_config_emu_unit()
59 		nitrox_write_csr(ndev, offset, emu_wd_int.value);  in nitrox_config_emu_unit()
61 		nitrox_write_csr(ndev, offset, emu_ge_int.value);  in nitrox_config_emu_unit()
74 	pkt_in_ctl.value = nitrox_read_csr(ndev, offset);  in reset_pkt_input_ring()
76 	nitrox_write_csr(ndev, offset, pkt_in_ctl.value);  in reset_pkt_input_ring()
81 		pkt_in_ctl.value = nitrox_read_csr(ndev, offset);  in reset_pkt_input_ring()
89 	pkt_in_cnts.value = nitrox_read_csr(ndev, offset);  in reset_pkt_input_ring()
90 	nitrox_write_csr(ndev, offset, pkt_in_cnts.value);  in reset_pkt_input_ring()
102 	pkt_in_ctl.value = nitrox_read_csr(ndev, offset);  in enable_pkt_input_ring()
105 	nitrox_write_csr(ndev, offset, pkt_in_ctl.value);  in enable_pkt_input_ring()
109 		pkt_in_ctl.value = nitrox_read_csr(ndev, offset);  in enable_pkt_input_ring()
142 		pkt_in_rsize.value = 0;  in nitrox_config_pkt_input_rings()
144 		nitrox_write_csr(ndev, offset, pkt_in_rsize.value);  in nitrox_config_pkt_input_rings()
152 		pkt_in_dbell.value = 0;  in nitrox_config_pkt_input_rings()
154 		nitrox_write_csr(ndev, offset, pkt_in_dbell.value);  in nitrox_config_pkt_input_rings()
170 	pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);  in reset_pkt_solicit_port()
172 	nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);  in reset_pkt_solicit_port()
178 		pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);  in reset_pkt_solicit_port()
186 	pkt_slc_cnts.value = nitrox_read_csr(ndev, offset);  in reset_pkt_solicit_port()
187 	nitrox_write_csr(ndev, offset, pkt_slc_cnts.value);  in reset_pkt_solicit_port()
198 	pkt_slc_ctl.value = 0;  in enable_pkt_solicit_port()
207 	nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);  in enable_pkt_solicit_port()
211 		pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);  in enable_pkt_solicit_port()
227 	pkt_slc_int.value = 0;  in config_pkt_solicit_port()
230 	nitrox_write_csr(ndev, offset, pkt_slc_int.value);  in config_pkt_solicit_port()
255 	core_int.value = 0;  in enable_nps_core_interrupts()
261 	nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value);  in enable_nps_core_interrupts()
272 	core_gbl_vfcfg.value = 0;  in nitrox_config_nps_core_unit()
275 	nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value);  in nitrox_config_nps_core_unit()
319 	aqmq_en_reg.value = 0;  in reset_aqm_ring()
321 	nitrox_write_csr(ndev, offset, aqmq_en_reg.value);  in reset_aqm_ring()
327 		activity_stat.value = nitrox_read_csr(ndev, offset);  in reset_aqm_ring()
335 	cmp_cnt.value = nitrox_read_csr(ndev, offset);  in reset_aqm_ring()
336 	nitrox_write_csr(ndev, offset, cmp_cnt.value);  in reset_aqm_ring()
346 	aqmq_en_reg.value = 0;  in enable_aqm_ring()
348 	nitrox_write_csr(ndev, offset, aqmq_en_reg.value);  in enable_aqm_ring()
368 		drbl.value = 0;  in nitrox_config_aqm_rings()
370 		nitrox_write_csr(ndev, offset, drbl.value);  in nitrox_config_aqm_rings()
384 		qsize.value = 0;  in nitrox_config_aqm_rings()
386 		nitrox_write_csr(ndev, offset, qsize.value);  in nitrox_config_aqm_rings()
390 		cmp_thr.value = 0;  in nitrox_config_aqm_rings()
392 		nitrox_write_csr(ndev, offset, cmp_thr.value);  in nitrox_config_aqm_rings()
427 	pom_int.value = 0;  in nitrox_config_pom_unit()
429 	nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value);  in nitrox_config_pom_unit()
446 	efl_rnm_ctl.value = nitrox_read_csr(ndev, offset);  in nitrox_config_rand_unit()
449 	nitrox_write_csr(ndev, offset, efl_rnm_ctl.value);  in nitrox_config_rand_unit()
462 		efl_core_int.value = 0;  in nitrox_config_efl_unit()
466 		nitrox_write_csr(ndev, offset, efl_core_int.value);  in nitrox_config_efl_unit()
483 	bmi_ctl.value = nitrox_read_csr(ndev, offset);  in nitrox_config_bmi_unit()
487 	nitrox_write_csr(ndev, offset, bmi_ctl.value);  in nitrox_config_bmi_unit()
491 	bmi_int_ena.value = 0;  in nitrox_config_bmi_unit()
495 	nitrox_write_csr(ndev, offset, bmi_int_ena.value);  in nitrox_config_bmi_unit()
505 	bmo_ctl2.value = nitrox_read_csr(ndev, offset);  in nitrox_config_bmo_unit()
507 	nitrox_write_csr(ndev, offset, bmo_ctl2.value);  in nitrox_config_bmo_unit()
519 	lbc_ctl.value = nitrox_read_csr(ndev, offset);  in invalidate_lbc()
521 	nitrox_write_csr(ndev, offset, lbc_ctl.value);  in invalidate_lbc()
525 		lbc_stat.value = nitrox_read_csr(ndev, offset);  in invalidate_lbc()
541 	lbc_int_ena.value = 0;  in nitrox_config_lbc_unit()
546 	nitrox_write_csr(ndev, offset, lbc_int_ena.value);  in nitrox_config_lbc_unit()
563 	vfcfg.value = nitrox_read_csr(ndev, NPS_CORE_GBL_VFCFG);  in config_nps_core_vfcfg_mode()
566 	nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, vfcfg.value);  in config_nps_core_vfcfg_mode()
619 	rst_boot.value = nitrox_read_csr(ndev, offset);  in nitrox_get_hwinfo()
624 		emu_fuse.value = nitrox_read_csr(ndev, offset);  in nitrox_get_hwinfo()
634 	fus_dat1.value = nitrox_read_csr(ndev, offset);  in nitrox_get_hwinfo()
655 	u64 value = ~0ULL;  in enable_pf2vf_mbox_interrupts()  local
660 	nitrox_write_csr(ndev, reg_addr, value);  in enable_pf2vf_mbox_interrupts()
664 	nitrox_write_csr(ndev, reg_addr, value);  in enable_pf2vf_mbox_interrupts()
669 	u64 value = ~0ULL;  in disable_pf2vf_mbox_interrupts()  local
674 	nitrox_write_csr(ndev, reg_addr, value);  in disable_pf2vf_mbox_interrupts()
678 	nitrox_write_csr(ndev, reg_addr, value);  in disable_pf2vf_mbox_interrupts()