27 			      u8 type, u8 grp)  in cpt_disable_cores()  argument
38 	grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp));  in cpt_disable_cores()
39 	cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp),  in cpt_disable_cores()
42 	grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0));  in cpt_disable_cores()
43 	while (grp & coremask) {  in cpt_disable_cores()
45 		grp = cpt_read_csr64(cpt->reg_base,  in cpt_disable_cores()
77 static void cpt_configure_group(struct cpt_device *cpt, u8 grp,  in cpt_configure_group()  argument
85 	pf_gx_en = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp));  in cpt_configure_group()
86 	cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp),  in cpt_configure_group()
383 	u32 grp, timeout = 100;  in cpt_disable_all_cores()  local
387 	for (grp = 0; grp < CPT_MAX_CORE_GROUPS; grp++) {  in cpt_disable_all_cores()
388 		cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), 0);  in cpt_disable_all_cores()
392 	grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0));  in cpt_disable_all_cores()
393 	while (grp) {  in cpt_disable_all_cores()
395 		grp = cpt_read_csr64(cpt->reg_base,  in cpt_disable_all_cores()
413 	u32 grp = 0, core;  in cpt_unload_microcode()  local
416 	for (grp = 0; grp < CPT_MAX_CORE_GROUPS; grp++) {  in cpt_unload_microcode()
417 		struct microcode *mcode = &cpt->mcode[grp];  in cpt_unload_microcode()
419 		if (cpt->mcode[grp].code)  in cpt_unload_microcode()