Lines Matching +full:zynqmp +full:- +full:aes
1 # SPDX-License-Identifier: GPL-2.0-only
29 tristate "PadLock driver for AES algorithm"
34 Use VIA PadLock for AES algorithm.
39 called padlock-aes.
53 called padlock-sha.
56 tristate "Support for the Geode LX AES engine"
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
62 engine for the CryptoAPI AES algorithm.
65 will be called geode-aes.
119 AES cipher algorithms for use with protected key.
131 and uses triple-DES to generate secure random numbers like the
132 ANSI X9.17 standard. User-space programs access the
133 pseudo-random-number device through the char device /dev/prandom.
149 sub-units. One set provides the Modular Arithmetic Unit,
250 This option provides the kernel-side support for the TRNG hardware
276 tristate "Support for OMAP AES hw engine"
286 OMAP processors have AES module accelerator. Select this if you
287 want to use the OMAP module for AES algorithms.
319 This driver provides kernel-side support through the
324 module will be called exynos-rng.
336 Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES
349 needed for small and zero-size messages.
371 Some Atmel processors can combine the AES and SHA hw accelerators
377 tristate "Support for Atmel AES hw accelerator"
385 Some Atmel processors have AES hw accelerator.
387 AES algorithms.
390 will be called atmel-aes.
403 will be called atmel-tdes.
416 will be called atmel-sha.
434 will be called atmel-ecc.
449 will be called atmel-sha204a.
473 co-processor on the die.
476 will be called mxs-dcp.
528 (default), hashes-only, or skciphers-only.
531 multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
535 algorithms, sharing the load with the CPU. Enabling skciphers-only
545 - AES (CBC, CTR, ECB, XTS)
546 - 3DES (CBC, ECB)
547 - DES (CBC, ECB)
548 - SHA1, HMAC-SHA1
549 - SHA256, HMAC-SHA256
552 bool "Symmetric-key ciphers only"
555 Enable symmetric-key ciphers only:
556 - AES (CBC, CTR, ECB, XTS)
557 - 3DES (ECB, CBC)
558 - DES (ECB, CBC)
565 - SHA1, HMAC-SHA1
566 - SHA256, HMAC-SHA256
573 - authenc()
574 - ccm(aes)
575 - rfc4309(ccm(aes))
579 int "Default maximum request size to use software for AES"
583 This sets the default maximum request size to perform AES requests
588 Considering the 256-bit ciphers, software is 2-3 times faster than
589 qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
590 With 128-bit keys, the break-even point would be around 1024-bytes.
593 cost in CPU usage. The minimum recommended setting is 16-bytes
594 (1 AES block), since AES-GCM will fail if you set it lower.
597 Note that 192-bit keys are not supported by the hardware and are
610 module will be called qcom-rng. If unsure, say N.
650 Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
663 tristate "Support for Xilinx ZynqMP AES hw accelerator"
669 Xilinx ZynqMP has AES-GCM engine used for symmetric key
670 encryption and decryption. This driver interfaces with AES hw
671 accelerator. Select this if you want to use the ZynqMP module
672 for AES algorithms.
675 tristate "Support for Xilinx ZynqMP SHA3 hardware accelerator"
679 Xilinx ZynqMP has SHA3 engine used for secure hash calculation.
681 Select this if you want to use the ZynqMP module
722 This driver interfaces with the SafeXcel EIP-97 and EIP-197 cryptographic
724 AES block ciphers in ECB and CBC mode, as well as SHA1, SHA224, SHA256,
726 Additionally, it accelerates combined AES-CBC/HMAC-SHA AEAD operations.
729 tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
742 Enables the driver for the on-chip crypto accelerator