1 // SPDX-License-Identifier: GPL-2.0
3  * STM32 Timer Encoder and Counter driver
11 #include <linux/mfd/stm32-timers.h>
52 	regmap_read(priv->regmap, TIM_CNT, &cnt);  in stm32_count_read()
64 	regmap_read(priv->regmap, TIM_ARR, &ceiling);  in stm32_count_write()
66 		return -EINVAL;  in stm32_count_write()
68 	return regmap_write(priv->regmap, TIM_CNT, val);  in stm32_count_write()
78 	regmap_read(priv->regmap, TIM_SMCR, &smcr);  in stm32_count_function_read()
94 		return -EINVAL;  in stm32_count_function_read()
119 		return -EINVAL;  in stm32_count_function_write()
123 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_function_write()
125 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_count_function_write()
127 	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);  in stm32_count_function_write()
130 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);  in stm32_count_function_write()
133 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);  in stm32_count_function_write()
145 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_direction_read()
158 	regmap_read(priv->regmap, TIM_ARR, &arr);  in stm32_count_ceiling_read()
170 	if (ceiling > priv->max_arr)  in stm32_count_ceiling_write()
171 		return -ERANGE;  in stm32_count_ceiling_write()
174 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);  in stm32_count_ceiling_write()
175 	regmap_write(priv->regmap, TIM_ARR, ceiling);  in stm32_count_ceiling_write()
186 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_enable_read()
201 		regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_enable_write()
203 			ret = clk_enable(priv->clk);  in stm32_count_enable_write()
205 				dev_err(counter->parent, "Cannot enable clock %d\n", ret);  in stm32_count_enable_write()
210 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,  in stm32_count_enable_write()
213 		regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_enable_write()
214 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_count_enable_write()
216 			clk_disable(priv->clk);  in stm32_count_enable_write()
220 	priv->enabled = enable;  in stm32_count_enable_write()
256 		if (synapse->signal->id == count->synapses[0].signal->id)  in stm32_action_read()
263 		if (synapse->signal->id == count->synapses[1].signal->id)  in stm32_action_read()
273 		return -EINVAL;  in stm32_action_read()
322 	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);  in stm32_timer_cnt_probe()
323 	struct device *dev = &pdev->dev;  in stm32_timer_cnt_probe()
329 		return -EINVAL;  in stm32_timer_cnt_probe()
333 		return -ENOMEM;  in stm32_timer_cnt_probe()
337 	priv->regmap = ddata->regmap;  in stm32_timer_cnt_probe()
338 	priv->clk = ddata->clk;  in stm32_timer_cnt_probe()
339 	priv->max_arr = ddata->max_arr;  in stm32_timer_cnt_probe()
341 	counter->name = dev_name(dev);  in stm32_timer_cnt_probe()
342 	counter->parent = dev;  in stm32_timer_cnt_probe()
343 	counter->ops = &stm32_timer_cnt_ops;  in stm32_timer_cnt_probe()
344 	counter->counts = &stm32_counts;  in stm32_timer_cnt_probe()
345 	counter->num_counts = 1;  in stm32_timer_cnt_probe()
346 	counter->signals = stm32_signals;  in stm32_timer_cnt_probe()
347 	counter->num_signals = ARRAY_SIZE(stm32_signals);  in stm32_timer_cnt_probe()
352 	regmap_write(priv->regmap, TIM_TISEL, 0x0);  in stm32_timer_cnt_probe()
367 	if (priv->enabled) {  in stm32_timer_cnt_suspend()
369 		regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);  in stm32_timer_cnt_suspend()
370 		regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);  in stm32_timer_cnt_suspend()
371 		regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);  in stm32_timer_cnt_suspend()
372 		regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);  in stm32_timer_cnt_suspend()
375 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_timer_cnt_suspend()
376 		clk_disable(priv->clk);  in stm32_timer_cnt_suspend()
391 	if (priv->enabled) {  in stm32_timer_cnt_resume()
392 		ret = clk_enable(priv->clk);  in stm32_timer_cnt_resume()
399 		regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);  in stm32_timer_cnt_resume()
400 		regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);  in stm32_timer_cnt_resume()
401 		regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);  in stm32_timer_cnt_resume()
403 		/* Also re-enables the counter */  in stm32_timer_cnt_resume()
404 		regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);  in stm32_timer_cnt_resume()
414 	{ .compatible = "st,stm32-timer-counter", },
422 		.name = "stm32-timer-counter",
430 MODULE_ALIAS("platform:stm32-timer-counter");
431 MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");