Lines Matching full:mmio
311 dev->mmio + DMA_LINE_CONTROL_GROUP1); in ni_pcidio_request_di_mite_channel()
327 dev->mmio + DMA_LINE_CONTROL_GROUP1); in ni_pcidio_release_di_mite_channel()
393 status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS); in nidio_interrupt()
394 flags = readb(dev->mmio + GROUP_1_FLAGS); in nidio_interrupt()
408 dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL); in nidio_interrupt()
420 writeb(0x00, dev->mmio + in nidio_interrupt()
425 auxdata = readl(dev->mmio + GROUP_1_FIFO); in nidio_interrupt()
427 flags = readb(dev->mmio + GROUP_1_FLAGS); in nidio_interrupt()
432 writeb(CLEAR_EXPIRED, dev->mmio + GROUP_1_SECOND_CLEAR); in nidio_interrupt()
435 writeb(0x00, dev->mmio + OP_MODE); in nidio_interrupt()
438 writeb(CLEAR_WAITED, dev->mmio + GROUP_1_FIRST_CLEAR); in nidio_interrupt()
443 dev->mmio + GROUP_1_FIRST_CLEAR); in nidio_interrupt()
447 dev->mmio + GROUP_1_FIRST_CLEAR); in nidio_interrupt()
451 flags = readb(dev->mmio + GROUP_1_FLAGS); in nidio_interrupt()
452 status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS); in nidio_interrupt()
459 writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL); in nidio_interrupt()
486 writel(s->io_bits, dev->mmio + PORT_PIN_DIRECTIONS(0)); in ni_pcidio_insn_config()
497 writel(s->state, dev->mmio + PORT_IO(0)); in ni_pcidio_insn_bits()
499 data[1] = readl(dev->mmio + PORT_IO(0)); in ni_pcidio_insn_bits()
611 writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE); in ni_pcidio_inttrig()
623 writel(0x0000, dev->mmio + PORT_PIN_DIRECTIONS(0)); in ni_pcidio_cmd()
627 writeb(0x0f, dev->mmio + DATA_PATH); in ni_pcidio_cmd()
631 dev->mmio + TRANSFER_SIZE_CONTROL); in ni_pcidio_cmd()
633 writeb(0x03, dev->mmio + DATA_PATH); in ni_pcidio_cmd()
635 dev->mmio + TRANSFER_SIZE_CONTROL); in ni_pcidio_cmd()
641 writeb(0, dev->mmio + OP_MODE); in ni_pcidio_cmd()
642 writeb(0x00, dev->mmio + CLOCK_REG); in ni_pcidio_cmd()
643 writeb(1, dev->mmio + SEQUENCE); in ni_pcidio_cmd()
644 writeb(0x04, dev->mmio + REQ_REG); in ni_pcidio_cmd()
645 writeb(4, dev->mmio + BLOCK_MODE); in ni_pcidio_cmd()
646 writeb(3, dev->mmio + LINE_POLARITIES); in ni_pcidio_cmd()
647 writeb(0xc0, dev->mmio + ACK_SER); in ni_pcidio_cmd()
650 dev->mmio + START_DELAY); in ni_pcidio_cmd()
651 writeb(1, dev->mmio + REQ_DELAY); in ni_pcidio_cmd()
652 writeb(1, dev->mmio + REQ_NOT_DELAY); in ni_pcidio_cmd()
653 writeb(1, dev->mmio + ACK_DELAY); in ni_pcidio_cmd()
654 writeb(0x0b, dev->mmio + ACK_NOT_DELAY); in ni_pcidio_cmd()
655 writeb(0x01, dev->mmio + DATA_1_DELAY); in ni_pcidio_cmd()
660 writew(0, dev->mmio + CLOCK_SPEED); in ni_pcidio_cmd()
661 writeb(0, dev->mmio + DAQ_OPTIONS); in ni_pcidio_cmd()
665 writeb(0, dev->mmio + OP_MODE); in ni_pcidio_cmd()
666 writeb(0x00, dev->mmio + CLOCK_REG); in ni_pcidio_cmd()
667 writeb(0, dev->mmio + SEQUENCE); in ni_pcidio_cmd()
668 writeb(0x00, dev->mmio + REQ_REG); in ni_pcidio_cmd()
669 writeb(4, dev->mmio + BLOCK_MODE); in ni_pcidio_cmd()
671 writeb(0, dev->mmio + LINE_POLARITIES); in ni_pcidio_cmd()
673 writeb(2, dev->mmio + LINE_POLARITIES); in ni_pcidio_cmd()
674 writeb(0x00, dev->mmio + ACK_SER); in ni_pcidio_cmd()
675 writel(1, dev->mmio + START_DELAY); in ni_pcidio_cmd()
676 writeb(1, dev->mmio + REQ_DELAY); in ni_pcidio_cmd()
677 writeb(1, dev->mmio + REQ_NOT_DELAY); in ni_pcidio_cmd()
678 writeb(1, dev->mmio + ACK_DELAY); in ni_pcidio_cmd()
679 writeb(0x0C, dev->mmio + ACK_NOT_DELAY); in ni_pcidio_cmd()
680 writeb(0x10, dev->mmio + DATA_1_DELAY); in ni_pcidio_cmd()
681 writew(0, dev->mmio + CLOCK_SPEED); in ni_pcidio_cmd()
682 writeb(0x60, dev->mmio + DAQ_OPTIONS); in ni_pcidio_cmd()
687 dev->mmio + TRANSFER_COUNT); in ni_pcidio_cmd()
694 dev->mmio + GROUP_1_FIRST_CLEAR); in ni_pcidio_cmd()
703 writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP1); in ni_pcidio_cmd()
705 writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP2); in ni_pcidio_cmd()
708 writeb(0xff, dev->mmio + GROUP_1_FIRST_CLEAR); in ni_pcidio_cmd()
709 /* writeb(CLEAR_EXPIRED, dev->mmio+GROUP_1_SECOND_CLEAR); */ in ni_pcidio_cmd()
711 writeb(INT_EN, dev->mmio + INTERRUPT_CONTROL); in ni_pcidio_cmd()
712 writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL); in ni_pcidio_cmd()
721 writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE); in ni_pcidio_cmd()
734 writeb(0x00, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL); in ni_pcidio_cancel()
764 writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register); in pci_6534_load_fpga()
765 writew(0xc0 | fpga_index, dev->mmio + Firmware_Control_Register); in pci_6534_load_fpga()
767 (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0 && in pci_6534_load_fpga()
777 writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register); in pci_6534_load_fpga()
779 readw(dev->mmio + Firmware_Status_Register) != 0x3 && in pci_6534_load_fpga()
793 writew(value, dev->mmio + Firmware_Data_Register); in pci_6534_load_fpga()
795 (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0 in pci_6534_load_fpga()
808 writew(0x0, dev->mmio + Firmware_Control_Register); in pci_6534_load_fpga()
822 writew(0x0, dev->mmio + Firmware_Control_Register); in pci_6534_reset_fpgas()
828 writew(0x0, dev->mmio + Firmware_Mask_Register); in pci_6534_reset_fpgas()
834 writel(0, dev->mmio + FPGA_Control1_Register); in pci_6534_init_main_fpga()
835 writel(0, dev->mmio + FPGA_Control2_Register); in pci_6534_init_main_fpga()
836 writel(0, dev->mmio + FPGA_SCALS_Counter_Register); in pci_6534_init_main_fpga()
837 writel(0, dev->mmio + FPGA_SCAMS_Counter_Register); in pci_6534_init_main_fpga()
838 writel(0, dev->mmio + FPGA_SCBLS_Counter_Register); in pci_6534_init_main_fpga()
839 writel(0, dev->mmio + FPGA_SCBMS_Counter_Register); in pci_6534_init_main_fpga()
871 writel(0, dev->mmio + PORT_IO(0)); in nidio_reset_board()
872 writel(0, dev->mmio + PORT_PIN_DIRECTIONS(0)); in nidio_reset_board()
873 writel(0, dev->mmio + PORT_PIN_MASK(0)); in nidio_reset_board()
876 writeb(0, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL); in nidio_reset_board()
927 readb(dev->mmio + CHIP_VERSION)); in nidio_auto_attach()
973 if (dev->mmio) in nidio_detach()
974 iounmap(dev->mmio); in nidio_detach()