294 	u32 tctl_val;  in imx1_gpt_setup_tctl()  local
296 	tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;  in imx1_gpt_setup_tctl()
297 	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);  in imx1_gpt_setup_tctl()
302 	u32 tctl_val;  in imx31_gpt_setup_tctl()  local
304 	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;  in imx31_gpt_setup_tctl()
306 		tctl_val |= V2_TCTL_CLK_OSC_DIV8;  in imx31_gpt_setup_tctl()
308 		tctl_val |= V2_TCTL_CLK_PER;  in imx31_gpt_setup_tctl()
310 	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);  in imx31_gpt_setup_tctl()
315 	u32 tctl_val;  in imx6dl_gpt_setup_tctl()  local
317 	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;  in imx6dl_gpt_setup_tctl()
319 		tctl_val |= V2_TCTL_CLK_OSC_DIV8;  in imx6dl_gpt_setup_tctl()
322 		tctl_val |= V2_TCTL_24MEN;  in imx6dl_gpt_setup_tctl()
324 		tctl_val |= V2_TCTL_CLK_PER;  in imx6dl_gpt_setup_tctl()
327 	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);  in imx6dl_gpt_setup_tctl()