1 // SPDX-License-Identifier: GPL-2.0
24  *   - Two channels combine to create a free-running 32 bit counter
27  *   - Some chips support 32 bit counter. A single channel is used for
28  *     this 32 bit free-running counter. the second channel is not used.
30  *   - The third channel may be used to provide a clockevent source, used in
31  *   either periodic or oneshot mode. For 16-bit counter its runs at 32 KiHZ,
32  *   and can handle delays of up to two seconds. For 32-bit counters, it runs at
163 	void __iomem		*regs = tcd->regs;  in tc_shutdown()
168 		clk_disable(tcd->clk);  in tc_shutdown()
176 	void __iomem		*regs = tcd->regs;  in tc_set_oneshot()
181 	clk_enable(tcd->clk);  in tc_set_oneshot()
195 	void __iomem		*regs = tcd->regs;  in tc_set_periodic()
203 	clk_enable(tcd->clk);  in tc_set_periodic()
208 	writel((tcd->rate + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));  in tc_set_periodic()
233 		/* Should be lower than at91rm9200's system timer */
247 	sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));  in ch2_irq()
249 		dev->clkevt.event_handler(&dev->clkevt);  in ch2_irq()
259 	struct clk *t2_clk = tc->clk[2];  in setup_clkevents()
260 	int irq = tc->irq[2];  in setup_clkevents()
261 	int bits = tc->tcb_config->counter_width;  in setup_clkevents()
268 	clkevt.regs = tc->regs;  in setup_clkevents()
275 		ret = clk_prepare_enable(tc->slow_clk);  in setup_clkevents()
281 		clkevt.rate = clk_get_rate(tc->slow_clk);  in setup_clkevents()
293 			clk_disable_unprepare(tc->slow_clk);  in setup_clkevents()
297 	clockevents_config_and_register(&clkevt.clkevt, clkevt.rate, 1, BIT(bits) - 1);  in setup_clkevents()
315 	writel(mck_divisor_idx			/* likely divide-by-8 */  in tcb_setup_dual_chan()
317 			| ATMEL_TC_WAVESEL_UP		/* free-run */  in tcb_setup_dual_chan()
330 			| ATMEL_TC_WAVESEL_UP,		/* free-run */  in tcb_setup_dual_chan()
344 	writel(mck_divisor_idx			/* likely divide-by-8 */  in tcb_setup_single_chan()
346 			| ATMEL_TC_WAVESEL_UP,		/* free-run */  in tcb_setup_single_chan()
369 	{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
370 	{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
371 	{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
382 	int best_divisor_idx = -1;  in tcb_clksrc_init()
391 	tc.regs = of_iomap(node->parent, 0);  in tcb_clksrc_init()
393 		return -ENXIO;  in tcb_clksrc_init()
395 	t0_clk = of_clk_get_by_name(node->parent, "t0_clk");  in tcb_clksrc_init()
399 	tc.slow_clk = of_clk_get_by_name(node->parent, "slow_clk");  in tcb_clksrc_init()
404 	tc.clk[1] = of_clk_get_by_name(node->parent, "t1_clk");  in tcb_clksrc_init()
407 	tc.clk[2] = of_clk_get_by_name(node->parent, "t2_clk");  in tcb_clksrc_init()
411 	tc.irq[2] = of_irq_get(node->parent, 2);  in tcb_clksrc_init()
413 		tc.irq[2] = of_irq_get(node->parent, 0);  in tcb_clksrc_init()
415 			return -EINVAL;  in tcb_clksrc_init()
418 	match = of_match_node(atmel_tcb_of_match, node->parent);  in tcb_clksrc_init()
420 		return -ENODEV;  in tcb_clksrc_init()
422 	tc.tcb_config = match->data;  in tcb_clksrc_init()
423 	bits = tc.tcb_config->counter_width;  in tcb_clksrc_init()
437 	if (tc.tcb_config->has_gclk)  in tcb_clksrc_init()
444 		pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);  in tcb_clksrc_init()
451 	clksrc.name = kbasename(node->parent->full_name);  in tcb_clksrc_init()
452 	clkevt.clkevt.name = kbasename(node->parent->full_name);  in tcb_clksrc_init()
511 TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init);