63 static void __iomem *mtu_base;  variable
76 	if (unlikely(!mtu_base))  in nomadik_read_sched_clock()
79 	return -readl(mtu_base + MTU_VAL(0));  in nomadik_read_sched_clock()
84 	return ~readl_relaxed(mtu_base + MTU_VAL(0));  in nmdk_timer_read_current_timer()
90 	writel(1 << 1, mtu_base + MTU_IMSC);  in nmdk_clkevt_next()
91 	writel(evt, mtu_base + MTU_LR(1));  in nmdk_clkevt_next()
95 	       mtu_base + MTU_CR(1));  in nmdk_clkevt_next()
104 		writel(nmdk_cycle, mtu_base + MTU_LR(1));  in nmdk_clkevt_reset()
105 		writel(nmdk_cycle, mtu_base + MTU_BGLR(1));  in nmdk_clkevt_reset()
109 		       mtu_base + MTU_CR(1));  in nmdk_clkevt_reset()
110 		writel(1 << 1, mtu_base + MTU_IMSC);  in nmdk_clkevt_reset()
119 	writel(0, mtu_base + MTU_IMSC);  in nmdk_clkevt_shutdown()
121 	writel(0, mtu_base + MTU_CR(1));  in nmdk_clkevt_shutdown()
123 	writel(0xffffffff, mtu_base + MTU_LR(1));  in nmdk_clkevt_shutdown()
143 	writel(0, mtu_base + MTU_CR(0));  in nmdk_clksrc_reset()
146 	writel(nmdk_cycle, mtu_base + MTU_LR(0));  in nmdk_clksrc_reset()
147 	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));  in nmdk_clksrc_reset()
150 	       mtu_base + MTU_CR(0));  in nmdk_clksrc_reset()
179 	writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */  in nmdk_timer_interrupt()
191 	mtu_base = base;  in nmdk_timer_init()
220 	ret = clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",  in nmdk_timer_init()