Lines Matching refs:WZRD_CLK_CFG_REG

26 #define WZRD_CLK_CFG_REG(n)	(0x200 + 4 * (n))  macro
278 	writel(reg, divider->base + WZRD_CLK_CFG_REG(2));  in clk_wzrd_dynamic_all_nolock()
282 	writel(reg, divider->base + WZRD_CLK_CFG_REG(0));  in clk_wzrd_dynamic_all_nolock()
283 	writel(divider->o, divider->base + WZRD_CLK_CFG_REG(2));  in clk_wzrd_dynamic_all_nolock()
284 	writel(0, divider->base + WZRD_CLK_CFG_REG(3));  in clk_wzrd_dynamic_all_nolock()
324 	reg = readl(divider->base + WZRD_CLK_CFG_REG(0));  in clk_wzrd_recalc_rate_all()
327 	reg = readl(divider->base + WZRD_CLK_CFG_REG(2));  in clk_wzrd_recalc_rate_all()
660 				clk_wzrd->base, WZRD_CLK_CFG_REG(3),  in clk_wzrd_probe()
669 	reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0));  in clk_wzrd_probe()
697 	ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(0);  in clk_wzrd_probe()
723 				clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),  in clk_wzrd_probe()
732 				clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),  in clk_wzrd_probe()