Lines Matching +full:flags +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
28 * FIXME need a mux-specific flag to determine if val is bitwise or in ti_clk_mux_get_parent()
34 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; in ti_clk_mux_get_parent()
35 val &= mux->mask; in ti_clk_mux_get_parent()
37 if (mux->table) { in ti_clk_mux_get_parent()
41 if (mux->table[i] == val) in ti_clk_mux_get_parent()
43 return -EINVAL; in ti_clk_mux_get_parent()
46 if (val && (mux->flags & CLK_MUX_INDEX_BIT)) in ti_clk_mux_get_parent()
47 val = ffs(val) - 1; in ti_clk_mux_get_parent()
49 if (val && (mux->flags & CLK_MUX_INDEX_ONE)) in ti_clk_mux_get_parent()
50 val--; in ti_clk_mux_get_parent()
53 return -EINVAL; in ti_clk_mux_get_parent()
63 if (mux->table) { in ti_clk_mux_set_parent()
64 index = mux->table[index]; in ti_clk_mux_set_parent()
66 if (mux->flags & CLK_MUX_INDEX_BIT) in ti_clk_mux_set_parent()
69 if (mux->flags & CLK_MUX_INDEX_ONE) in ti_clk_mux_set_parent()
73 if (mux->flags & CLK_MUX_HIWORD_MASK) { in ti_clk_mux_set_parent()
74 val = mux->mask << (mux->shift + 16); in ti_clk_mux_set_parent()
76 val = ti_clk_ll_ops->clk_readl(&mux->reg); in ti_clk_mux_set_parent()
77 val &= ~(mux->mask << mux->shift); in ti_clk_mux_set_parent()
79 val |= index << mux->shift; in ti_clk_mux_set_parent()
80 ti_clk_ll_ops->clk_writel(val, &mux->reg); in ti_clk_mux_set_parent()
81 ti_clk_latch(&mux->reg, mux->latch); in ti_clk_mux_set_parent()
87 * clk_mux_save_context - Save the parent selcted in the mux
96 mux->saved_parent = ti_clk_mux_get_parent(hw); in clk_mux_save_context()
101 * clk_mux_restore_context - Restore the parent in the mux
110 ti_clk_mux_set_parent(hw, mux->saved_parent); in clk_mux_restore_context()
123 u8 num_parents, unsigned long flags, in _register_mux() argument
124 struct clk_omap_reg *reg, u8 shift, u32 mask, in _register_mux() argument
134 return ERR_PTR(-ENOMEM); in _register_mux()
138 init.flags = flags; in _register_mux()
143 memcpy(&mux->reg, reg, sizeof(*reg)); in _register_mux()
144 mux->shift = shift; in _register_mux()
145 mux->mask = mask; in _register_mux()
146 mux->latch = latch; in _register_mux()
147 mux->flags = clk_mux_flags; in _register_mux()
148 mux->table = table; in _register_mux()
149 mux->hw.init = &init; in _register_mux()
151 clk = of_ti_clk_register(node, &mux->hw, name); in _register_mux()
160 * of_mux_clk_setup - Setup function for simple mux rate clock
173 u32 mask = 0; in of_mux_clk_setup() local
175 s32 latch = -EINVAL; in of_mux_clk_setup()
176 u32 flags = CLK_SET_RATE_NO_REPARENT; in of_mux_clk_setup() local
180 pr_err("mux-clock %pOFn must have parents\n", node); in of_mux_clk_setup()
192 of_property_read_u32(node, "ti,bit-shift", &shift); in of_mux_clk_setup()
194 of_property_read_u32(node, "ti,latch-bit", &latch); in of_mux_clk_setup()
196 if (of_property_read_bool(node, "ti,index-starts-at-one")) in of_mux_clk_setup()
199 if (of_property_read_bool(node, "ti,set-rate-parent")) in of_mux_clk_setup()
200 flags |= CLK_SET_RATE_PARENT; in of_mux_clk_setup()
202 /* Generate bit-mask based on parent info */ in of_mux_clk_setup()
203 mask = num_parents; in of_mux_clk_setup()
205 mask--; in of_mux_clk_setup()
207 mask = (1 << fls(mask)) - 1; in of_mux_clk_setup()
211 flags, ®, shift, mask, latch, clk_mux_flags, in of_mux_clk_setup()
220 CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
232 return ERR_PTR(-ENOMEM); in ti_clk_build_component_mux()
234 mux->shift = setup->bit_shift; in ti_clk_build_component_mux()
235 mux->latch = -EINVAL; in ti_clk_build_component_mux()
237 mux->reg.index = setup->module; in ti_clk_build_component_mux()
238 mux->reg.offset = setup->reg; in ti_clk_build_component_mux()
240 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE) in ti_clk_build_component_mux()
241 mux->flags |= CLK_MUX_INDEX_ONE; in ti_clk_build_component_mux()
243 num_parents = setup->num_parents; in ti_clk_build_component_mux()
245 mux->mask = num_parents - 1; in ti_clk_build_component_mux()
246 mux->mask = (1 << fls(mux->mask)) - 1; in ti_clk_build_component_mux()
248 return &mux->hw; in ti_clk_build_component_mux()
261 if (ti_clk_get_reg_addr(node, 0, &mux->reg)) in of_ti_composite_mux_clk_setup()
264 if (!of_property_read_u32(node, "ti,bit-shift", &val)) in of_ti_composite_mux_clk_setup()
265 mux->shift = val; in of_ti_composite_mux_clk_setup()
267 if (of_property_read_bool(node, "ti,index-starts-at-one")) in of_ti_composite_mux_clk_setup()
268 mux->flags |= CLK_MUX_INDEX_ONE; in of_ti_composite_mux_clk_setup()
277 mux->mask = num_parents - 1; in of_ti_composite_mux_clk_setup()
278 mux->mask = (1 << fls(mux->mask)) - 1; in of_ti_composite_mux_clk_setup()
280 if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX)) in of_ti_composite_mux_clk_setup()
286 CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",