49 	const struct dpll_data *dd;  in _omap3_dpll_write_clken()  local
52 	dd = clk->dpll_data;  in _omap3_dpll_write_clken()
54 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in _omap3_dpll_write_clken()
55 	v &= ~dd->enable_mask;  in _omap3_dpll_write_clken()
56 	v |= clken_bits << __ffs(dd->enable_mask);  in _omap3_dpll_write_clken()
57 	ti_clk_ll_ops->clk_writel(v, &dd->control_reg);  in _omap3_dpll_write_clken()
63 	const struct dpll_data *dd;  in _omap3_wait_dpll_status()  local
68 	dd = clk->dpll_data;  in _omap3_wait_dpll_status()
71 	state <<= __ffs(dd->idlest_mask);  in _omap3_wait_dpll_status()
73 	while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask)  in _omap3_wait_dpll_status()
140 	const struct dpll_data *dd;  in _omap3_noncore_dpll_lock()  local
147 	dd = clk->dpll_data;  in _omap3_noncore_dpll_lock()
148 	state <<= __ffs(dd->idlest_mask);  in _omap3_noncore_dpll_lock()
151 	if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) ==  in _omap3_noncore_dpll_lock()
303 	struct dpll_data *dd = clk->dpll_data;  in omap3_noncore_dpll_ssc_program()  local
308 	ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap3_noncore_dpll_ssc_program()
310 	if (dd->ssc_modfreq && dd->ssc_deltam) {  in omap3_noncore_dpll_ssc_program()
311 		ctrl |= dd->ssc_enable_mask;  in omap3_noncore_dpll_ssc_program()
313 		if (dd->ssc_downspread)  in omap3_noncore_dpll_ssc_program()
314 			ctrl |= dd->ssc_downspread_mask;  in omap3_noncore_dpll_ssc_program()
316 			ctrl &= ~dd->ssc_downspread_mask;  in omap3_noncore_dpll_ssc_program()
318 		ref_rate = clk_hw_get_rate(dd->clk_ref);  in omap3_noncore_dpll_ssc_program()
320 		    (ref_rate / dd->last_rounded_n) / (4 * dd->ssc_modfreq);  in omap3_noncore_dpll_ssc_program()
321 		if (dd->ssc_modfreq > (ref_rate / 70))  in omap3_noncore_dpll_ssc_program()
334 		v = ti_clk_ll_ops->clk_readl(&dd->ssc_modfreq_reg);  in omap3_noncore_dpll_ssc_program()
335 		v &= ~(dd->ssc_modfreq_mant_mask | dd->ssc_modfreq_exp_mask);  in omap3_noncore_dpll_ssc_program()
336 		v |= mantissa << __ffs(dd->ssc_modfreq_mant_mask);  in omap3_noncore_dpll_ssc_program()
337 		v |= exponent << __ffs(dd->ssc_modfreq_exp_mask);  in omap3_noncore_dpll_ssc_program()
338 		ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg);  in omap3_noncore_dpll_ssc_program()
340 		deltam_step = dd->last_rounded_m * dd->ssc_deltam;  in omap3_noncore_dpll_ssc_program()
342 		if (dd->ssc_downspread)  in omap3_noncore_dpll_ssc_program()
345 		deltam_step <<= __ffs(dd->ssc_deltam_int_mask);  in omap3_noncore_dpll_ssc_program()
351 		deltam_ceil = (deltam_step & dd->ssc_deltam_int_mask) >>  in omap3_noncore_dpll_ssc_program()
352 		    __ffs(dd->ssc_deltam_int_mask);  in omap3_noncore_dpll_ssc_program()
353 		if (deltam_step & dd->ssc_deltam_frac_mask)  in omap3_noncore_dpll_ssc_program()
356 		if ((dd->ssc_downspread &&  in omap3_noncore_dpll_ssc_program()
357 		     ((dd->last_rounded_m - (2 * deltam_ceil)) < 20 ||  in omap3_noncore_dpll_ssc_program()
358 		      dd->last_rounded_m > 2045)) ||  in omap3_noncore_dpll_ssc_program()
359 		    ((dd->last_rounded_m - deltam_ceil) < 20 ||  in omap3_noncore_dpll_ssc_program()
360 		     (dd->last_rounded_m + deltam_ceil) > 2045))  in omap3_noncore_dpll_ssc_program()
364 		v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg);  in omap3_noncore_dpll_ssc_program()
365 		v &= ~(dd->ssc_deltam_int_mask | dd->ssc_deltam_frac_mask);  in omap3_noncore_dpll_ssc_program()
366 		v |= deltam_step << __ffs(dd->ssc_deltam_int_mask |  in omap3_noncore_dpll_ssc_program()
367 					  dd->ssc_deltam_frac_mask);  in omap3_noncore_dpll_ssc_program()
368 		ti_clk_ll_ops->clk_writel(v, &dd->ssc_deltam_reg);  in omap3_noncore_dpll_ssc_program()
370 		ctrl &= ~dd->ssc_enable_mask;  in omap3_noncore_dpll_ssc_program()
373 	ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg);  in omap3_noncore_dpll_ssc_program()
386 	struct dpll_data *dd = clk->dpll_data;  in omap3_noncore_dpll_program()  local
399 		v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap3_noncore_dpll_program()
400 		v &= ~dd->freqsel_mask;  in omap3_noncore_dpll_program()
401 		v |= freqsel << __ffs(dd->freqsel_mask);  in omap3_noncore_dpll_program()
402 		ti_clk_ll_ops->clk_writel(v, &dd->control_reg);  in omap3_noncore_dpll_program()
406 	v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);  in omap3_noncore_dpll_program()
409 	if (dd->dcc_mask) {  in omap3_noncore_dpll_program()
410 		if (dd->last_rounded_rate >= dd->dcc_rate)  in omap3_noncore_dpll_program()
411 			v |= dd->dcc_mask; /* Enable DCC */  in omap3_noncore_dpll_program()
413 			v &= ~dd->dcc_mask; /* Disable DCC */  in omap3_noncore_dpll_program()
416 	v &= ~(dd->mult_mask | dd->div1_mask);  in omap3_noncore_dpll_program()
417 	v |= dd->last_rounded_m << __ffs(dd->mult_mask);  in omap3_noncore_dpll_program()
418 	v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);  in omap3_noncore_dpll_program()
421 	if (dd->dco_mask) {  in omap3_noncore_dpll_program()
422 		_lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);  in omap3_noncore_dpll_program()
423 		v &= ~(dd->dco_mask);  in omap3_noncore_dpll_program()
424 		v |= dco << __ffs(dd->dco_mask);  in omap3_noncore_dpll_program()
426 	if (dd->sddiv_mask) {  in omap3_noncore_dpll_program()
427 		_lookup_sddiv(clk, &sd_div, dd->last_rounded_m,  in omap3_noncore_dpll_program()
428 			      dd->last_rounded_n);  in omap3_noncore_dpll_program()
429 		v &= ~(dd->sddiv_mask);  in omap3_noncore_dpll_program()
430 		v |= sd_div << __ffs(dd->sddiv_mask);  in omap3_noncore_dpll_program()
452 	ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);  in omap3_noncore_dpll_program()
455 	if (dd->m4xen_mask || dd->lpmode_mask) {  in omap3_noncore_dpll_program()
456 		v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap3_noncore_dpll_program()
458 		if (dd->m4xen_mask) {  in omap3_noncore_dpll_program()
459 			if (dd->last_rounded_m4xen)  in omap3_noncore_dpll_program()
460 				v |= dd->m4xen_mask;  in omap3_noncore_dpll_program()
462 				v &= ~dd->m4xen_mask;  in omap3_noncore_dpll_program()
465 		if (dd->lpmode_mask) {  in omap3_noncore_dpll_program()
466 			if (dd->last_rounded_lpmode)  in omap3_noncore_dpll_program()
467 				v |= dd->lpmode_mask;  in omap3_noncore_dpll_program()
469 				v &= ~dd->lpmode_mask;  in omap3_noncore_dpll_program()
472 		ti_clk_ll_ops->clk_writel(v, &dd->control_reg);  in omap3_noncore_dpll_program()
475 	if (dd->ssc_enable_mask)  in omap3_noncore_dpll_program()
526 	struct dpll_data *dd;  in omap3_noncore_dpll_enable()  local
529 	dd = clk->dpll_data;  in omap3_noncore_dpll_enable()
530 	if (!dd)  in omap3_noncore_dpll_enable()
546 	if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) {  in omap3_noncore_dpll_enable()
547 		WARN_ON(parent != dd->clk_bypass);  in omap3_noncore_dpll_enable()
550 		WARN_ON(parent != dd->clk_ref);  in omap3_noncore_dpll_enable()
589 	struct dpll_data *dd;  in omap3_noncore_dpll_determine_rate()  local
594 	dd = clk->dpll_data;  in omap3_noncore_dpll_determine_rate()
595 	if (!dd)  in omap3_noncore_dpll_determine_rate()
598 	if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&  in omap3_noncore_dpll_determine_rate()
599 	    (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {  in omap3_noncore_dpll_determine_rate()
600 		req->best_parent_hw = dd->clk_bypass;  in omap3_noncore_dpll_determine_rate()
604 		req->best_parent_hw = dd->clk_ref;  in omap3_noncore_dpll_determine_rate()
651 	struct dpll_data *dd;  in omap3_noncore_dpll_set_rate()  local
658 	dd = clk->dpll_data;  in omap3_noncore_dpll_set_rate()
659 	if (!dd)  in omap3_noncore_dpll_set_rate()
662 	if (clk_hw_get_parent(hw) != dd->clk_ref)  in omap3_noncore_dpll_set_rate()
665 	if (dd->last_rounded_rate == 0)  in omap3_noncore_dpll_set_rate()
670 		freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);  in omap3_noncore_dpll_set_rate()
730 	const struct dpll_data *dd;  in omap3_dpll_autoidle_read()  local
736 	dd = clk->dpll_data;  in omap3_dpll_autoidle_read()
738 	if (!dd->autoidle_mask)  in omap3_dpll_autoidle_read()
741 	v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);  in omap3_dpll_autoidle_read()
742 	v &= dd->autoidle_mask;  in omap3_dpll_autoidle_read()
743 	v >>= __ffs(dd->autoidle_mask);  in omap3_dpll_autoidle_read()
759 	const struct dpll_data *dd;  in omap3_dpll_allow_idle()  local
765 	dd = clk->dpll_data;  in omap3_dpll_allow_idle()
767 	if (!dd->autoidle_mask)  in omap3_dpll_allow_idle()
775 	v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);  in omap3_dpll_allow_idle()
776 	v &= ~dd->autoidle_mask;  in omap3_dpll_allow_idle()
777 	v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);  in omap3_dpll_allow_idle()
778 	ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);  in omap3_dpll_allow_idle()
789 	const struct dpll_data *dd;  in omap3_dpll_deny_idle()  local
795 	dd = clk->dpll_data;  in omap3_dpll_deny_idle()
797 	if (!dd->autoidle_mask)  in omap3_dpll_deny_idle()
800 	v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);  in omap3_dpll_deny_idle()
801 	v &= ~dd->autoidle_mask;  in omap3_dpll_deny_idle()
802 	v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);  in omap3_dpll_deny_idle()
803 	ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);  in omap3_dpll_deny_idle()
843 	const struct dpll_data *dd;  in omap3_clkoutx2_recalc()  local
856 	dd = pclk->dpll_data;  in omap3_clkoutx2_recalc()
858 	WARN_ON(!dd->enable_mask);  in omap3_clkoutx2_recalc()
860 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;  in omap3_clkoutx2_recalc()
861 	v >>= __ffs(dd->enable_mask);  in omap3_clkoutx2_recalc()
862 	if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))  in omap3_clkoutx2_recalc()
879 	struct dpll_data *dd;  in omap3_core_dpll_save_context()  local
882 	dd = clk->dpll_data;  in omap3_core_dpll_save_context()
884 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap3_core_dpll_save_context()
885 	clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);  in omap3_core_dpll_save_context()
888 		v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);  in omap3_core_dpll_save_context()
889 		dd->last_rounded_m = (v & dd->mult_mask) >>  in omap3_core_dpll_save_context()
890 						__ffs(dd->mult_mask);  in omap3_core_dpll_save_context()
891 		dd->last_rounded_n = ((v & dd->div1_mask) >>  in omap3_core_dpll_save_context()
892 						__ffs(dd->div1_mask)) + 1;  in omap3_core_dpll_save_context()
908 	const struct dpll_data *dd;  in omap3_core_dpll_restore_context()  local
911 	dd = clk->dpll_data;  in omap3_core_dpll_restore_context()
917 		v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);  in omap3_core_dpll_restore_context()
918 		v &= ~(dd->mult_mask | dd->div1_mask);  in omap3_core_dpll_restore_context()
919 		v |= dd->last_rounded_m << __ffs(dd->mult_mask);  in omap3_core_dpll_restore_context()
920 		v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);  in omap3_core_dpll_restore_context()
921 		ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);  in omap3_core_dpll_restore_context()
940 	struct dpll_data *dd;  in omap3_noncore_dpll_save_context()  local
943 	dd = clk->dpll_data;  in omap3_noncore_dpll_save_context()
945 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap3_noncore_dpll_save_context()
946 	clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);  in omap3_noncore_dpll_save_context()
949 		v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);  in omap3_noncore_dpll_save_context()
950 		dd->last_rounded_m = (v & dd->mult_mask) >>  in omap3_noncore_dpll_save_context()
951 						__ffs(dd->mult_mask);  in omap3_noncore_dpll_save_context()
952 		dd->last_rounded_n = ((v & dd->div1_mask) >>  in omap3_noncore_dpll_save_context()
953 						__ffs(dd->div1_mask)) + 1;  in omap3_noncore_dpll_save_context()
969 	const struct dpll_data *dd;  in omap3_noncore_dpll_restore_context()  local
972 	dd = clk->dpll_data;  in omap3_noncore_dpll_restore_context()
974 	ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap3_noncore_dpll_restore_context()
975 	mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);  in omap3_noncore_dpll_restore_context()
977 	if (clk->context == ((ctrl & dd->enable_mask) >>  in omap3_noncore_dpll_restore_context()
978 			     __ffs(dd->enable_mask)) &&  in omap3_noncore_dpll_restore_context()
979 	    dd->last_rounded_m == ((mult_div1 & dd->mult_mask) >>  in omap3_noncore_dpll_restore_context()
980 				   __ffs(dd->mult_mask)) &&  in omap3_noncore_dpll_restore_context()
981 	    dd->last_rounded_n == ((mult_div1 & dd->div1_mask) >>  in omap3_noncore_dpll_restore_context()
982 				   __ffs(dd->div1_mask)) + 1) {  in omap3_noncore_dpll_restore_context()
1074 	struct dpll_data *dd;  in omap3_dpll5_apply_errata()  local
1088 	dd = clk->dpll_data;  in omap3_dpll5_apply_errata()
1089 	dd->last_rounded_m = d->m;  in omap3_dpll5_apply_errata()
1090 	dd->last_rounded_n = d->n;  in omap3_dpll5_apply_errata()
1091 	dd->last_rounded_rate = div_u64((u64)parent_rate * d->m, d->n);  in omap3_dpll5_apply_errata()