3  * OMAP3/4 - specific DPLL control functions
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
129  * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
130  * @clk: pointer to a DPLL struct clk
132  * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
133  * readiness before returning.  Will save and restore the DPLL's
134  * autoidle state across the enable, per the CDP code.  If the DPLL
135  * locked successfully, return 0; if the DPLL did not lock in the time
145 	pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw));  in _omap3_noncore_dpll_lock()
172  * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
173  * @clk: pointer to a DPLL struct clk
175  * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
176  * bypass mode, the DPLL's rate is set equal to its parent clock's
177  * rate.  Waits for the DPLL to report readiness before returning.
178  * Will save and restore the DPLL's autoidle state across the enable,
179  * per the CDP code.  If the DPLL entered bypass mode successfully,
180  * return 0; if the DPLL did not enter bypass in the time allotted, or
181  * DPLL3 was passed in, or the DPLL does not support low-power bypass,
192 	pr_debug("clock: configuring DPLL %s for low-power bypass\n",  in _omap3_noncore_dpll_bypass()
208  * _omap3_noncore_dpll_stop - instruct a DPLL to stop
209  * @clk: pointer to a DPLL struct clk
211  * Instructs a non-CORE DPLL to enter low-power stop. Will save and
212  * restore the DPLL's autoidle state across the stop, per the CDP
213  * code.  If DPLL3 was passed in, or the DPLL does not support
223 	pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw));  in _omap3_noncore_dpll_stop()
236  * _lookup_dco - Lookup DCO used by j-type DPLL
237  * @clk: pointer to a DPLL struct clk
239  * @m: DPLL multiplier to set
240  * @n: DPLL divider to set
242  * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
261  * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
262  * @clk: pointer to a DPLL struct clk
264  * @m: DPLL multiplier to set
265  * @n: DPLL divider to set
267  * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
296  * @clk:	struct clk * of DPLL to set
298  * Enable the DPLL spread spectrum clocking if frequency modulation and
322 			pr_warn("clock: SSC modulation frequency of DPLL %s greater than %ld\n",  in omap3_noncore_dpll_ssc_program()
361 			pr_warn("clock: SSC multiplier of DPLL %s is out of range\n",  in omap3_noncore_dpll_ssc_program()
377  * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
378  * @clk:	struct clk * of DPLL to set
381  * Program the DPLL with the last M, N values calculated, and wait for
382  * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success.
391 	/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */  in omap3_noncore_dpll_program()
405 	/* Set DPLL multiplier, divider */  in omap3_noncore_dpll_program()
434 	 * Errata i810 - DPLL controller can get stuck while transitioning  in omap3_noncore_dpll_program()
435 	 * to a power saving state. Software must ensure the DPLL can not  in omap3_noncore_dpll_program()
437 	 * Easiest way to accomplish this is to prevent DPLL autoidle  in omap3_noncore_dpll_program()
493  * omap3_dpll_recalc - recalculate DPLL rate
494  * @hw: struct clk_hw containing the DPLL struct clk
495  * @parent_rate: clock rate of the DPLL parent
497  * Recalculate and propagate the DPLL rate.
506 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
509  * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
510  * @hw: struct clk_hw containing then pointer to a DPLL struct clk
512  * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
513  * The choice of modes depends on the DPLL's programmed rate: if it is
514  * the same as the DPLL's parent clock, it will enter bypass;
515  * otherwise, it will enter lock.  This code will wait for the DPLL to
516  * indicate readiness before returning, unless the DPLL takes too long
518  * enable function.  If DPLL3 was passed in, or the DPLL does not
519  * support low-power stop, or if the DPLL took too long to enter
558  * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
559  * @hw: struct clk_hw containing then pointer to a DPLL struct clk
561  * Instructs a non-CORE DPLL to enter low-power stop.  This function is
573 /* Non-CORE DPLL rate set code */
576  * omap3_noncore_dpll_determine_rate - determine rate for a DPLL
580  * Determines which DPLL mode to use for reaching a desired target rate.
581  * Checks whether the DPLL shall be in bypass or locked mode, and if
582  * locked, calculates the M,N values for the DPLL via round-rate.
613  * omap3_noncore_dpll_set_parent - set parent for a DPLL clock
617  * Sets parent for a DPLL clock. This sets the DPLL into bypass or
637  * omap3_noncore_dpll_set_rate - set rate for a DPLL clock
642  * Sets rate for a DPLL clock. First checks if the clock parent is
683  * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock
685  * @rate: target rate for the DPLL
686  * @parent_rate: clock rate of the DPLL parent
687  * @index: new parent index for the DPLL, 0 - reference, 1 - bypass
689  * Sets rate and parent for a DPLL clock. If new parent is the bypass
692  * DPLL is put into locked mode. Returns 0 with success, negative error
718 /* DPLL autoidle read/set code */
721  * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
722  * @clk: struct clk * of the DPLL to read
724  * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
726  * appear to refer to a DPLL.
749  * omap3_dpll_allow_idle - enable DPLL autoidle bits
750  * @clk: struct clk * of the DPLL to operate on
752  * Enable DPLL automatic idle control.  This automatic idle mode
753  * switching takes effect only when the DPLL is locked, at least on
754  * OMAP3430.  The DPLL will enter low-power stop when its downstream
771 	 * REVISIT: CORE DPLL can optionally enter low-power bypass  in omap3_dpll_allow_idle()
782  * omap3_dpll_deny_idle - prevent DPLL from automatically idling
783  * @clk: struct clk * of the DPLL to operate on
785  * Disable DPLL automatic idle control.  No return value.
806 /* Clock control for DPLL outputs */
808 /* Find the parent DPLL for the given clkoutx2 clock */
813 	/* Walk up the parents of clk, looking for a DPLL */  in omap3_find_clkoutx2_dpll()
823 	/* clk does not have a DPLL as a parent?  error in the clock data */  in omap3_find_clkoutx2_dpll()
833  * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
835  * @parent_rate: clock rate of the DPLL parent
837  * Using parent clock DPLL data, look up DPLL state.  If locked, set our
873  * Before the dpll registers are lost save the last rounded rate m and n
934  * Before the dpll registers are lost save the last rounded rate m and n
993 /* OMAP3/4 non-CORE DPLL clkops */
1000  * omap3_dpll4_set_rate - set rate for omap3 per-dpll
1003  * @parent_rate: clock rate of the DPLL parent
1005  * Check if the current SoC supports the per-dpll reprogram operation
1015 	 * on 3430ES1 prevents us from changing DPLL multipliers or dividers  in omap3_dpll4_set_rate()
1027  * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
1033  * Check if the current SoC support the per-dpll reprogram operation
1087 	/* Update the M, N and rounded rate values and program the DPLL. */  in omap3_dpll5_apply_errata()
1104  * the DPLL is used for USB host (detected through the requested rate).