22 static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
27 static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
32 static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
38 static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
43 static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
48 static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
56 static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
74 static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
81 static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
97 static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
102 static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
107 static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
112 static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
117 static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
123 static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
128 static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
139 static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
144 static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
149 static const char * const dra7_cam_gfclk_mux_parents[] __initconst = {
155 static const struct omap_clkctrl_bit_data dra7_cam_bit_data[] __initconst = {
160 static const struct omap_clkctrl_reg_data dra7_cam_clkctrl_regs[] __initconst = {
167 static const struct omap_clkctrl_reg_data dra7_vpe_clkctrl_regs[] __initconst = {
172 static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
178 static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
189 static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {
194 static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
199 static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
204 static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
212 static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
219 static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
225 static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
230 static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
249 static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
255 static const struct omap_clkctrl_reg_data dra7_iva_clkctrl_regs[] __initconst = {
261 static const char * const dra7_dss_dss_clk_parents[] __initconst = {
266 static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
271 static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
276 static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
281 static const char * const dra7_dss_video1_clk_parents[] __initconst = {
286 static const char * const dra7_dss_video2_clk_parents[] __initconst = {
291 static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
301 static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
307 static const char * const dra7_gpu_core_mux_parents[] __initconst = {
314 static const char * const dra7_gpu_hyd_mux_parents[] __initconst = {
321 static const struct omap_clkctrl_bit_data dra7_gpu_core_bit_data[] __initconst = {
327 static const struct omap_clkctrl_reg_data dra7_gpu_clkctrl_regs[] __initconst = {
332 static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
338 static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
343 static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {  variable
348 static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
355 static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
360 static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {  variable
365 static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
372 static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
377 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
382 static const char * const dra7_sata_ref_clk_parents[] __initconst = {
387 static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
392 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
397 static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
410 static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
415 static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
420 static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
427 static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
434 static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = {
440 static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
446 static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
455 static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
461 static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
466 static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
481 static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
486 static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
491 static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
496 static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
501 static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
506 static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
511 static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
516 static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
521 static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
526 static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
531 static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
536 static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
541 static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
546 static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
551 static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {  variable
556 static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
563 static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
568 static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {  variable
573 static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
580 static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
585 static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
590 static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
595 static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
600 static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
605 static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
640 static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = {
650 static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
656 static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
661 static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {  variable
666 static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
672 static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
679 static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
685 static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
691 static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
697 static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
703 static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
708 static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
713 static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
718 static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
724 static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
730 static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = {
752 static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
757 static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
762 static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
767 static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
772 static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = {
781 static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
786 static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
791 static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
796 static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
802 static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
807 static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
820 const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {