184 static struct clk **clks;
815 	struct clk *clk;  in tegra30_pll_init()  local
818 	clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",  in tegra30_pll_init()
821 	clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",  in tegra30_pll_init()
824 	clks[TEGRA30_CLK_PLL_C_OUT1] = clk;  in tegra30_pll_init()
827 	clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",  in tegra30_pll_init()
830 	clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",  in tegra30_pll_init()
833 	clks[TEGRA30_CLK_PLL_M_OUT1] = clk;  in tegra30_pll_init()
836 	clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
838 	clks[TEGRA30_CLK_PLL_X] = clk;  in tegra30_pll_init()
841 	clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",  in tegra30_pll_init()
843 	clks[TEGRA30_CLK_PLL_X_OUT0] = clk;  in tegra30_pll_init()
846 	clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0,  in tegra30_pll_init()
848 	clks[TEGRA30_CLK_PLL_U] = clk;  in tegra30_pll_init()
851 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
853 	clks[TEGRA30_CLK_PLL_D] = clk;  in tegra30_pll_init()
856 	clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",  in tegra30_pll_init()
858 	clks[TEGRA30_CLK_PLL_D_OUT0] = clk;  in tegra30_pll_init()
861 	clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
863 	clks[TEGRA30_CLK_PLL_D2] = clk;  in tegra30_pll_init()
866 	clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",  in tegra30_pll_init()
868 	clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;  in tegra30_pll_init()
871 	clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,  in tegra30_pll_init()
890 	struct clk *clk;  in tegra30_super_clk_init()  local
896 	clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",  in tegra30_super_clk_init()
899 	clk_register_clkdev(clk, "pll_p_cclkg", NULL);  in tegra30_super_clk_init()
905 	clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",  in tegra30_super_clk_init()
908 	clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);  in tegra30_super_clk_init()
914 	clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",  in tegra30_super_clk_init()
917 	clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);  in tegra30_super_clk_init()
920 	clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents,  in tegra30_super_clk_init()
925 	clks[TEGRA30_CLK_CCLK_G] = clk;  in tegra30_super_clk_init()
931 	clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",  in tegra30_super_clk_init()
934 	clk_register_clkdev(clk, "pll_p_cclklp", NULL);  in tegra30_super_clk_init()
940 	clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",  in tegra30_super_clk_init()
943 	clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);  in tegra30_super_clk_init()
949 	clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",  in tegra30_super_clk_init()
952 	clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);  in tegra30_super_clk_init()
955 	clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,  in tegra30_super_clk_init()
961 	clks[TEGRA30_CLK_CCLK_LP] = clk;  in tegra30_super_clk_init()
964 	clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",  in tegra30_super_clk_init()
966 	clks[TEGRA30_CLK_TWD] = clk;  in tegra30_super_clk_init()
1003 	struct clk *clk;  in tegra30_periph_clk_init()  local
1007 	clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,  in tegra30_periph_clk_init()
1009 	clks[TEGRA30_CLK_DSIA] = clk;  in tegra30_periph_clk_init()
1012 	clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,  in tegra30_periph_clk_init()
1014 	clks[TEGRA30_CLK_PCIE] = clk;  in tegra30_periph_clk_init()
1017 	clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,  in tegra30_periph_clk_init()
1019 	clks[TEGRA30_CLK_AFI] = clk;  in tegra30_periph_clk_init()
1022 	clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true);  in tegra30_periph_clk_init()
1024 	clks[TEGRA30_CLK_EMC] = clk;  in tegra30_periph_clk_init()
1026 	clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,  in tegra30_periph_clk_init()
1028 	clks[TEGRA30_CLK_MC] = clk;  in tegra30_periph_clk_init()
1031 	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,  in tegra30_periph_clk_init()
1033 	clks[TEGRA30_CLK_CML0] = clk;  in tegra30_periph_clk_init()
1036 	clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,  in tegra30_periph_clk_init()
1038 	clks[TEGRA30_CLK_CML1] = clk;  in tegra30_periph_clk_init()
1042 		clk = tegra_clk_register_periph_data(clk_base, data);  in tegra30_periph_clk_init()
1043 		clks[data->clk_id] = clk;  in tegra30_periph_clk_init()
1048 		clk = tegra_clk_register_periph_nodiv(data->name,  in tegra30_periph_clk_init()
1052 		clks[data->clk_id] = clk;  in tegra30_periph_clk_init()
1276 static struct clk *tegra30_clk_src_onecell_get(struct of_phandle_args *clkspec,  in tegra30_clk_src_onecell_get()
1280 	struct clk *clk;  in tegra30_clk_src_onecell_get()  local
1292 	clk = of_clk_src_onecell_get(clkspec, data);  in tegra30_clk_src_onecell_get()
1293 	if (IS_ERR(clk))  in tegra30_clk_src_onecell_get()
1294 		return clk;  in tegra30_clk_src_onecell_get()
1296 	hw = __clk_get_hw(clk);  in tegra30_clk_src_onecell_get()
1303 	return clk;  in tegra30_clk_src_onecell_get()
1366 	struct clk *clk;  in tegra30_car_probe()  local
1369 	clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,  in tegra30_car_probe()
1371 	clks[TEGRA30_CLK_PLL_C] = clk;  in tegra30_car_probe()
1374 	clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,  in tegra30_car_probe()
1376 	clks[TEGRA30_CLK_PLL_E] = clk;  in tegra30_car_probe()
1379 	clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,  in tegra30_car_probe()
1381 	clks[TEGRA30_CLK_PLL_M] = clk;  in tegra30_car_probe()
1384 	clk = tegra_clk_register_super_mux("sclk", sclk_parents,  in tegra30_car_probe()
1389 	clks[TEGRA30_CLK_SCLK] = clk;  in tegra30_car_probe()