Lines Matching refs:TEGRA20_CLK_PLL_P
422 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
549 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },
1013 { TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
1025 { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 },
1026 { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 },
1027 { TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
1028 { TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
1029 { TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
1034 { TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
1035 { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
1036 { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
1037 { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
1038 { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
1039 { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
1040 { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
1041 { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 },
1046 { TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 },