clk/tegra/clk-tegra124.c

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (c) 2012-2014 NVIDIA CORPORATION.  All rights reserved.
7 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/tegra124-car.h>
15 #include <dt-bindings/reset/tegra124-car.h>
18 #include "clk-id.h"
95 #define MASK(x) (BIT(x) - 1)
138 	[ 8] = 12000000,
173 	{ 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
182 	.input_min = 12000000,
184 	.cf_min = 12000000,
206 	{ 12000000, 624000000, 104, 1, 2, 0 },
207 	{ 12000000, 600000000, 100, 1, 2, 0 },
216 	.input_min = 12000000,
218 	.cf_min = 12000000,
261 	{ 12000000, 600000000, 100, 1, 2, 0 },
270 	.input_min = 12000000,
272 	.cf_min = 12000000,
292 	.input_min = 12000000,
294 	.cf_min = 12000000,
342 	{ 12000000, 600000000, 100, 1, 2, 0 },
351 	.input_min = 12000000,
353 	.cf_min = 12000000,
393 	{ 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
414 	.input_min = 12000000,
416 	.cf_min = 12000000,
438 	{  12000000, 100000000, 200,  1, 24, 13 },
471 	.input_min = 12000000,
473 	.cf_min = 12000000,
510 	.input_min = 12000000,
512 	.cf_min = 12000000,
538 	{ 12000000, 408000000, 408, 12, 1, 8 },
603 	{ 12000000,  216000000,  864, 12, 4, 12 },
608 	{ 12000000,  594000000,  594, 12, 1, 12 },
613 	{ 12000000, 1000000000, 1000, 12, 1, 12 },
639 	{ 12000000, 594000000, 99, 1, 2, 0 },
648 	.input_min = 12000000,
650 	.cf_min = 12000000,
672 	{ 12000000, 600000000, 100, 1, 2, 0 },
681 	.input_min = 12000000,
683 	.cf_min = 12000000,
720 	{ 12000000, 480000000, 960, 12, 2, 12 },
995 	{ .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
1073 		clkp = tegra_lookup_dt_id(init->clk_id, tegra124_clks);  in tegra124_periph_clk_init()
1075 			pr_warn("clock %u not found\n", init->clk_id);  in tegra124_periph_clk_init()
1286 	{ .compatible = "nvidia,tegra124-pmc" },
1311 	{ TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1 },
1359  * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
1363  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1373  * tegra124_car_barrier - wait for pending writes to the CAR to complete
1384  * tegra124_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1399  * tegra124_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1419 		return -EINVAL;  in tegra124_reset_assert()
1429 		return -EINVAL;  in tegra124_reset_deassert()
1435  * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs
1439  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1449  * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
1517 	if (clkspec->args[0] == TEGRA124_CLK_EMC) {  in tegra124_clk_src_onecell_get()
1519 			return ERR_PTR(-EPROBE_DEFER);  in tegra124_clk_src_onecell_get()
1526  * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
1552  * tegra124_clock_init - Tegra124-specific clock initialization
1555  * Register most SoC clocks for the Tegra124 system-on-chip.  Most of
1559  * "nvidia,tegra124-car" string is encountered, and declared with
1570  * tegra132_clock_init - Tegra132-specific clock initialization
1573  * Register most SoC clocks for the Tegra132 system-on-chip.  Most of
1577  * "nvidia,tegra132-car" string is encountered, and declared with
1596 CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
1597 CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init);