Lines Matching +full:- +full:1 +full:ul
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
21 #include "clk-dfll.h"
33 [0] = 2014500000UL,
34 [1] = 2320500000UL,
35 [2] = 2116500000UL,
36 [3] = 2524500000UL,
41 .speedo_id = -1,
42 .process_id = -1,
48 { 204000000UL, { 1112619, -29295, 402 } },
49 { 306000000UL, { 1150460, -30585, 402 } },
50 { 408000000UL, { 1190122, -31865, 402 } },
51 { 510000000UL, { 1231606, -33155, 402 } },
52 { 612000000UL, { 1274912, -34435, 402 } },
53 { 714000000UL, { 1320040, -35725, 402 } },
54 { 816000000UL, { 1366990, -37005, 402 } },
55 { 918000000UL, { 1415762, -38295, 402 } },
56 { 1020000000UL, { 1466355, -39575, 402 } },
57 { 1122000000UL, { 1518771, -40865, 402 } },
58 { 1224000000UL, { 1573009, -42145, 402 } },
59 { 1326000000UL, { 1629068, -43435, 402 } },
60 { 1428000000UL, { 1686950, -44715, 402 } },
61 { 1530000000UL, { 1746653, -46005, 402 } },
62 { 1632000000UL, { 1808179, -47285, 402 } },
63 { 1734000000UL, { 1871526, -48575, 402 } },
64 { 1836000000UL, { 1936696, -49855, 402 } },
65 { 1938000000UL, { 2003687, -51145, 402 } },
66 { 2014500000UL, { 2054787, -52095, 402 } },
67 { 2116500000UL, { 2124957, -53385, 402 } },
68 { 2218500000UL, { 2196950, -54665, 402 } },
69 { 2320500000UL, { 2270765, -55955, 402 } },
70 { 2422500000UL, { 2346401, -57235, 402 } },
71 { 2524500000UL, { 2437299, -58535, 402 } },
72 { 0UL, { 0, 0, 0 } },
83 [0] = 1912500000UL,
84 [1] = 1912500000UL,
85 [2] = 2218500000UL,
86 [3] = 1785000000UL,
87 [4] = 1632000000UL,
88 [5] = 1912500000UL,
89 [6] = 2014500000UL,
90 [7] = 1734000000UL,
91 [8] = 1683000000UL,
92 [9] = 1555500000UL,
93 [10] = 1504500000UL,
100 { 204000000UL, { 1007452, -23865, 370 } }, \
101 { 306000000UL, { 1052709, -24875, 370 } }, \
102 { 408000000UL, { 1099069, -25895, 370 } }, \
103 { 510000000UL, { 1146534, -26905, 370 } }, \
104 { 612000000UL, { 1195102, -27915, 370 } }, \
105 { 714000000UL, { 1244773, -28925, 370 } }, \
106 { 816000000UL, { 1295549, -29935, 370 } }, \
107 { 918000000UL, { 1347428, -30955, 370 } }, \
108 { 1020000000UL, { 1400411, -31965, 370 } }, \
109 { 1122000000UL, { 1454497, -32975, 370 } }, \
110 { 1224000000UL, { 1509687, -33985, 370 } }, \
111 { 1326000000UL, { 1565981, -35005, 370 } }, \
112 { 1428000000UL, { 1623379, -36015, 370 } }, \
113 { 1530000000UL, { 1681880, -37025, 370 } }, \
114 { 1632000000UL, { 1741485, -38035, 370 } }, \
115 { 1734000000UL, { 1802194, -39055, 370 } }, \
116 { 1836000000UL, { 1864006, -40065, 370 } }, \
117 { 1912500000UL, { 1910780, -40815, 370 } }, \
118 { 2014500000UL, { 1227000, 0, 0 } }, \
119 { 2218500000UL, { 1227000, 0, 0 } }, \
120 { 0UL, { 0, 0, 0 } }, \
127 { 204000000UL, { 1250024, -39785, 565 } }, \
128 { 306000000UL, { 1297556, -41145, 565 } }, \
129 { 408000000UL, { 1346718, -42505, 565 } }, \
130 { 510000000UL, { 1397511, -43855, 565 } }, \
131 { 612000000UL, { 1449933, -45215, 565 } }, \
132 { 714000000UL, { 1503986, -46575, 565 } }, \
133 { 816000000UL, { 1559669, -47935, 565 } }, \
134 { 918000000UL, { 1616982, -49295, 565 } }, \
135 { 1020000000UL, { 1675926, -50645, 565 } }, \
136 { 1122000000UL, { 1736500, -52005, 565 } }, \
137 { 1224000000UL, { 1798704, -53365, 565 } }, \
138 { 1326000000UL, { 1862538, -54725, 565 } }, \
139 { 1428000000UL, { 1928003, -56085, 565 } }, \
140 { 1530000000UL, { 1995097, -57435, 565 } }, \
141 { 1606500000UL, { 2046149, -58445, 565 } }, \
142 { 1632000000UL, { 2063822, -58795, 565 } }, \
143 { 0UL, { 0, 0, 0 } }, \
150 { 204000000UL, { 734429, 0, 0 } }, \
151 { 306000000UL, { 768191, 0, 0 } }, \
152 { 408000000UL, { 801953, 0, 0 } }, \
153 { 510000000UL, { 835715, 0, 0 } }, \
154 { 612000000UL, { 869477, 0, 0 } }, \
155 { 714000000UL, { 903239, 0, 0 } }, \
156 { 816000000UL, { 937001, 0, 0 } }, \
157 { 918000000UL, { 970763, 0, 0 } }, \
158 { 1020000000UL, { 1004525, 0, 0 } }, \
159 { 1122000000UL, { 1038287, 0, 0 } }, \
160 { 1224000000UL, { 1072049, 0, 0 } }, \
161 { 1326000000UL, { 1105811, 0, 0 } }, \
162 { 1428000000UL, { 1130000, 0, 0 } }, \
163 { 1555500000UL, { 1130000, 0, 0 } }, \
164 { 1632000000UL, { 1170000, 0, 0 } }, \
165 { 1734000000UL, { 1227500, 0, 0 } }, \
166 { 0UL, { 0, 0, 0 } }, \
173 { 204000000UL, { 742283, 0, 0 } }, \
174 { 306000000UL, { 776249, 0, 0 } }, \
175 { 408000000UL, { 810215, 0, 0 } }, \
176 { 510000000UL, { 844181, 0, 0 } }, \
177 { 612000000UL, { 878147, 0, 0 } }, \
178 { 714000000UL, { 912113, 0, 0 } }, \
179 { 816000000UL, { 946079, 0, 0 } }, \
180 { 918000000UL, { 980045, 0, 0 } }, \
181 { 1020000000UL, { 1014011, 0, 0 } }, \
182 { 1122000000UL, { 1047977, 0, 0 } }, \
183 { 1224000000UL, { 1081943, 0, 0 } }, \
184 { 1326000000UL, { 1090000, 0, 0 } }, \
185 { 1479000000UL, { 1090000, 0, 0 } }, \
186 { 1555500000UL, { 1162000, 0, 0 } }, \
187 { 1683000000UL, { 1195000, 0, 0 } }, \
188 { 0UL, { 0, 0, 0 } }, \
195 { 204000000UL, { 742283, 0, 0 } }, \
196 { 306000000UL, { 776249, 0, 0 } }, \
197 { 408000000UL, { 810215, 0, 0 } }, \
198 { 510000000UL, { 844181, 0, 0 } }, \
199 { 612000000UL, { 878147, 0, 0 } }, \
200 { 714000000UL, { 912113, 0, 0 } }, \
201 { 816000000UL, { 946079, 0, 0 } }, \
202 { 918000000UL, { 980045, 0, 0 } }, \
203 { 1020000000UL, { 1014011, 0, 0 } }, \
204 { 1122000000UL, { 1047977, 0, 0 } }, \
205 { 1224000000UL, { 1081943, 0, 0 } }, \
206 { 1326000000UL, { 1090000, 0, 0 } }, \
207 { 1479000000UL, { 1090000, 0, 0 } }, \
208 { 1504500000UL, { 1120000, 0, 0 } }, \
209 { 0UL, { 0, 0, 0 } }, \
216 { 204000000UL, { 721094, 0, 0 } }, \
217 { 306000000UL, { 754040, 0, 0 } }, \
218 { 408000000UL, { 786986, 0, 0 } }, \
219 { 510000000UL, { 819932, 0, 0 } }, \
220 { 612000000UL, { 852878, 0, 0 } }, \
221 { 714000000UL, { 885824, 0, 0 } }, \
222 { 816000000UL, { 918770, 0, 0 } }, \
223 { 918000000UL, { 915716, 0, 0 } }, \
224 { 1020000000UL, { 984662, 0, 0 } }, \
225 { 1122000000UL, { 1017608, 0, 0 } }, \
226 { 1224000000UL, { 1050554, 0, 0 } }, \
227 { 1326000000UL, { 1083500, 0, 0 } }, \
228 { 1428000000UL, { 1116446, 0, 0 } }, \
229 { 1581000000UL, { 1130000, 0, 0 } }, \
230 { 1683000000UL, { 1168000, 0, 0 } }, \
231 { 1785000000UL, { 1227500, 0, 0 } }, \
232 { 0UL, { 0, 0, 0 } }, \
251 .process_id = 1,
276 .process_id = 1,
300 .process_id = 1,
325 .process_id = 1,
349 .process_id = 1,
373 .process_id = 1,
386 .process_id = -1,
410 .process_id = 1,
434 .process_id = 1,
444 .speedo_id = 1,
457 .speedo_id = 1,
458 .process_id = 1,
484 .process_id = 1,
513 .compatible = "nvidia,tegra124-dfll",
517 .compatible = "nvidia,tegra210-dfll",
526 if (of_property_read_u32(dev->of_node, in get_alignment_from_dt()
527 "nvidia,pwm-voltage-step-microvolts", in get_alignment_from_dt()
528 &align->step_uv)) in get_alignment_from_dt()
529 align->step_uv = 0; in get_alignment_from_dt()
531 if (of_property_read_u32(dev->of_node, in get_alignment_from_dt()
532 "nvidia,pwm-min-microvolts", in get_alignment_from_dt()
533 &align->offset_uv)) in get_alignment_from_dt()
534 align->offset_uv = 0; in get_alignment_from_dt()
540 struct regulator *reg = regulator_get(dev, "vdd-cpu"); in get_alignment_from_regulator()
545 align->offset_uv = regulator_list_voltage(reg, 0); in get_alignment_from_regulator()
546 align->step_uv = regulator_get_linear_step(reg); in get_alignment_from_regulator()
560 fcpu_data = of_device_get_match_data(&pdev->dev); in tegra124_dfll_fcpu_probe()
562 return -ENODEV; in tegra124_dfll_fcpu_probe()
568 if (speedo_id >= fcpu_data->cpu_max_freq_table_size) { in tegra124_dfll_fcpu_probe()
569 dev_err(&pdev->dev, "unknown max CPU freq for speedo_id=%d\n", in tegra124_dfll_fcpu_probe()
571 return -ENODEV; in tegra124_dfll_fcpu_probe()
574 soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL); in tegra124_dfll_fcpu_probe()
576 return -ENOMEM; in tegra124_dfll_fcpu_probe()
578 soc->dev = get_cpu_device(0); in tegra124_dfll_fcpu_probe()
579 if (!soc->dev) { in tegra124_dfll_fcpu_probe()
580 dev_err(&pdev->dev, "no CPU0 device\n"); in tegra124_dfll_fcpu_probe()
581 return -ENODEV; in tegra124_dfll_fcpu_probe()
584 if (of_property_read_bool(pdev->dev.of_node, "nvidia,pwm-to-pmic")) { in tegra124_dfll_fcpu_probe()
585 get_alignment_from_dt(&pdev->dev, &align); in tegra124_dfll_fcpu_probe()
587 err = get_alignment_from_regulator(&pdev->dev, &align); in tegra124_dfll_fcpu_probe()
592 soc->max_freq = fcpu_data->cpu_max_freq_table[speedo_id]; in tegra124_dfll_fcpu_probe()
594 soc->cvb = tegra_cvb_add_opp_table(soc->dev, fcpu_data->cpu_cvb_tables, in tegra124_dfll_fcpu_probe()
595 fcpu_data->cpu_cvb_tables_size, in tegra124_dfll_fcpu_probe()
597 speedo_value, soc->max_freq); in tegra124_dfll_fcpu_probe()
598 soc->alignment = align; in tegra124_dfll_fcpu_probe()
600 if (IS_ERR(soc->cvb)) { in tegra124_dfll_fcpu_probe()
601 dev_err(&pdev->dev, "couldn't add OPP table: %ld\n", in tegra124_dfll_fcpu_probe()
602 PTR_ERR(soc->cvb)); in tegra124_dfll_fcpu_probe()
603 return PTR_ERR(soc->cvb); in tegra124_dfll_fcpu_probe()
608 tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq); in tegra124_dfll_fcpu_probe()
627 tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq); in tegra124_dfll_fcpu_remove()
640 .name = "tegra124-dfll",