clk/tegra/clk-tegra114.c

1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/tegra114-car.h>
16 #include "clk-id.h"
20 #define CPU_FINETRIM_DR			0x4d8	/* rise->rise prop dly A */
21 #define CPU_FINETRIM_R			0x4e4	/* rise->rise prop dly inc A */
168 	{ 12000000, 624000000, 104, 1, 2, 0 },
169 	{ 12000000, 600000000, 100, 1, 2, 0 },
178 	.input_min = 12000000,
180 	.cf_min = 12000000,
220 	{ 12000000, 600000000, 100, 1, 2, 0 },
229 	.input_min = 12000000,
231 	.cf_min = 12000000,
251 	.input_min = 12000000,
253 	.cf_min = 12000000,
291 	{ 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
300 	.input_min = 12000000,
302 	.cf_min = 12000000,
331 	{ 12000000, 216000000, 432, 12, 2, 8 },
388 	{ 12000000,  216000000,  864, 12, 4, 12 },
393 	{ 12000000,  594000000,  594, 12, 1, 12 },
398 	{ 12000000, 1000000000, 1000, 12, 1, 12 },
457 	{ 12000000, 480000000, 960, 12, 2, 12 },
486 	{ 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
495 	.input_min = 12000000,
497 	.cf_min = 12000000,
522 	{  12000000, 100000000, 200,  1, 24, 13 },
555 	.input_min = 12000000,
557 	.cf_min = 12000000,
584 	.input_min = 12000000,
586 	.cf_min = 12000000,
608 	[ 8] = 12000000,
613 #define MASK(x) (BIT(x) - 1)
870 	{ .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
1059 	clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,  in tegra114_periph_clk_init()
1067 		clks[data->clk_id] = clk;  in tegra114_periph_clk_init()
1126 	{ .compatible = "nvidia,tegra114-pmc" },
1180  * tegra114_car_barrier - wait for pending writes to the CAR to complete
1192  * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
1194  * When the CPU rail voltage is in the high-voltage range, use the
1195  * built-in hardwired clock propagation delays in the CPU clock
1202 	/* Use hardwired rise->rise & fall->fall clock propagation delays */  in tegra114_clock_tune_cpu_trimmers_high()
1213  * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
1215  * When the CPU rail voltage is in the low-voltage range, use the
1226 	 * Use software-specified rise->rise & fall->fall clock  in tegra114_clock_tune_cpu_trimmers_low()
1240  * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
1243  * shaper and enable them.  XXX Define the purpose - peak current
1251 	/* Increment the rise->rise clock delay by four steps */  in tegra114_clock_tune_cpu_trimmers_init()
1258 	 * Use the rise->rise clock propagation delay specified in the  in tegra114_clock_tune_cpu_trimmers_init()
1271  * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1287  * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1354 CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);