260 struct tegra_dfll {  struct
262 	struct tegra_dfll_soc_data	*soc;  argument
264 	void __iomem			*base;
265 	void __iomem			*i2c_base;
266 	void __iomem			*i2c_controller_base;
267 	void __iomem			*lut_base;
269 	struct regulator		*vdd_reg;
270 	struct clk			*soc_clk;
271 	struct clk			*ref_clk;
272 	struct clk			*i2c_clk;
273 	struct clk			*dfll_clk;
274 	struct reset_control		*dfll_rst;
275 	struct reset_control		*dvco_rst;
276 	unsigned long			ref_rate;
277 	unsigned long			i2c_clk_rate;
278 	unsigned long			dvco_rate_min;
280 	enum dfll_ctrl_mode		mode;
281 	enum dfll_tune_range		tune_range;
282 	struct dentry			*debugfs_dir;
283 	struct clk_hw			dfll_clk_hw;
284 	const char			*output_clock_name;
285 	struct dfll_rate_req		last_req;
309 	enum tegra_dfll_pmu_if		pmu_if;  argument
317 #define clk_hw_to_dfll(_hw) container_of(_hw, struct tegra_dfll, dfll_clk_hw)  argument