clk/tegra/clk-device.c

1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk-provider.h>
18  * This driver manages performance state of the core power domain for the
33 	struct device *dev = clk_dev->dev;  in tegra_clock_set_pd_state()
38 	if (opp == ERR_PTR(-ERANGE)) {  in tegra_clock_set_pd_state()
41 		 * may have uninitiated clock rate that is overly high.  In  in tegra_clock_set_pd_state()
43 		 * need to set up performance state of the power domain and  in tegra_clock_set_pd_state()
71 	mutex_lock(&clk_dev->lock);  in tegra_clock_change_notify()
74 		if (cnd->new_rate > cnd->old_rate)  in tegra_clock_change_notify()
75 			err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate);  in tegra_clock_change_notify()
79 		err = tegra_clock_set_pd_state(clk_dev, cnd->old_rate);  in tegra_clock_change_notify()
83 		if (cnd->new_rate < cnd->old_rate)  in tegra_clock_change_notify()
84 			err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate);  in tegra_clock_change_notify()
90 	mutex_unlock(&clk_dev->lock);  in tegra_clock_change_notify()
100 	mutex_lock(&clk_dev->lock);  in tegra_clock_sync_pd_state()
102 	rate = clk_hw_get_rate(clk_dev->hw);  in tegra_clock_sync_pd_state()
105 	mutex_unlock(&clk_dev->lock);  in tegra_clock_sync_pd_state()
114 	struct device *dev = &pdev->dev;  in tegra_clock_probe()
118 	if (!dev->pm_domain)  in tegra_clock_probe()
119 		return -EINVAL;  in tegra_clock_probe()
123 		return -ENOMEM;  in tegra_clock_probe()
129 	clk_dev->dev = dev;  in tegra_clock_probe()
130 	clk_dev->hw = __clk_get_hw(clk);  in tegra_clock_probe()
131 	clk_dev->clk_nb.notifier_call = tegra_clock_change_notify;  in tegra_clock_probe()
132 	mutex_init(&clk_dev->lock);  in tegra_clock_probe()
138 	 * driver and power domain state should be synced under clk_dev lock,  in tegra_clock_probe()
147 	err = clk_notifier_register(clk, &clk_dev->clk_nb);  in tegra_clock_probe()
155 	 * we need to sync the power domain performance state in a accordance to  in tegra_clock_probe()
165 	clk_notifier_unregister(clk, &clk_dev->clk_nb);  in tegra_clock_probe()
172  * for clocks served by this driver because runtime PM is unavailable in
173  * NOIRQ phase. We will keep clocks resumed during suspend to mitigate this
174  * problem. In practice this makes no difference from a power management
175  * perspective since voltage is kept at a nominal level during suspend anyways.
182 	{ .compatible = "nvidia,tegra20-sclk" },
183 	{ .compatible = "nvidia,tegra30-sclk" },
184 	{ .compatible = "nvidia,tegra30-pllc" },
185 	{ .compatible = "nvidia,tegra30-plle" },
186 	{ .compatible = "nvidia,tegra30-pllm" },
192 		.name = "tegra-clock",