Lines Matching +full:0 +full:xb0
44 .reg = 0x00,
49 0),
53 static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0);
55 static SUNXI_CCU_M(apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
64 apb0_gate_parent, 0x28, BIT(0), 0);
66 apb0_gate_parent, 0x28, BIT(1), 0);
68 apb0_gate_parent, 0x28, BIT(2), 0);
70 apb0_gate_parent, 0x28, BIT(3), 0);
72 apb0_gate_parent, 0x28, BIT(4), 0);
74 apb0_gate_parent, 0x28, BIT(6), 0);
76 apb0_gate_parent, 0x28, BIT(7), 0);
80 r_mod0_default_parents, 0x54,
81 0, 4, /* M */
85 0);
92 { .index = 0, .div = 16 },
97 .m = _SUNXI_CCU_DIV(0, 4),
108 .reg = 0x54,
113 0),
182 [RST_APB0_IR] = { 0xb0, BIT(1) },
183 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
184 [RST_APB0_RSB] = { 0xb0, BIT(3) },
185 [RST_APB0_UART] = { 0xb0, BIT(4) },
186 [RST_APB0_I2C] = { 0xb0, BIT(6) },
190 [RST_APB0_IR] = { 0xb0, BIT(1) },
191 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
192 [RST_APB0_UART] = { 0xb0, BIT(4) },
193 [RST_APB0_I2C] = { 0xb0, BIT(6) },
197 [RST_APB0_IR] = { 0xb0, BIT(1) },
198 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
199 [RST_APB0_RSB] = { 0xb0, BIT(3) },
200 [RST_APB0_UART] = { 0xb0, BIT(4) },
201 [RST_APB0_I2C] = { 0xb0, BIT(6) },
243 reg = devm_platform_ioremap_resource(pdev, 0); in sun8i_r_ccu_probe()