Lines Matching +full:24 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-a23-a33.h"
27 .enable = BIT(31),
28 .lock = BIT(28),
37 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
62 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
66 pll_audio_sdm_table, BIT(24),
67 0x284, BIT(31),
68 BIT(31), /* gate */
69 BIT(28), /* lock */
72 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
76 BIT(24), /* frac enable */
77 BIT(25), /* frac select */
80 BIT(31), /* gate */
81 BIT(28), /* lock */
84 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
88 BIT(24), /* frac enable */
89 BIT(25), /* frac select */
92 BIT(31), /* gate */
93 BIT(28), /* lock */
96 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
101 BIT(31), /* gate */
102 BIT(28), /* lock */
105 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
109 BIT(31), /* gate */
110 BIT(28), /* lock */
111 2, /* post-div */
114 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
118 BIT(24), /* frac enable */
119 BIT(25), /* frac select */
122 BIT(31), /* gate */
123 BIT(28), /* lock */
129 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
134 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
135 "pll-video", 0x040,
139 BIT(31) | BIT(23) | BIT(22), /* gate */
140 BIT(28), /* lock */
143 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
147 BIT(24), /* frac enable */
148 BIT(25), /* frac select */
151 BIT(31), /* gate */
152 BIT(28), /* lock */
155 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
159 BIT(24), /* frac enable */
160 BIT(25), /* frac select */
163 BIT(31), /* gate */
164 BIT(28), /* lock */
168 .enable = BIT(31),
169 .lock = BIT(28),
173 .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M",
180 "pll-cpux" , "pll-cpux" };
187 "axi" , "pll-periph" };
223 "pll-periph" , "pll-periph" };
227 24, 2, /* mux */
230 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
231 0x060, BIT(1), 0);
232 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
233 0x060, BIT(5), 0);
234 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
235 0x060, BIT(6), 0);
236 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
237 0x060, BIT(8), 0);
238 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
239 0x060, BIT(9), 0);
240 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
241 0x060, BIT(10), 0);
242 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
243 0x060, BIT(13), 0);
244 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
245 0x060, BIT(14), 0);
246 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
247 0x060, BIT(19), 0);
248 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
249 0x060, BIT(20), 0);
250 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
251 0x060, BIT(21), 0);
252 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
253 0x060, BIT(24), 0);
254 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
255 0x060, BIT(26), 0);
256 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
257 0x060, BIT(29), 0);
259 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
260 0x064, BIT(0), 0);
261 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
262 0x064, BIT(4), 0);
263 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
264 0x064, BIT(8), 0);
265 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
266 0x064, BIT(12), 0);
267 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
268 0x064, BIT(14), 0);
269 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
270 0x064, BIT(20), 0);
271 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
272 0x064, BIT(21), 0);
273 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
274 0x064, BIT(22), 0);
275 static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
276 0x064, BIT(25), 0);
277 static SUNXI_CCU_GATE(bus_sat_clk, "bus-sat", "ahb1",
278 0x064, BIT(26), 0);
280 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
281 0x068, BIT(0), 0);
282 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
283 0x068, BIT(5), 0);
284 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
285 0x068, BIT(12), 0);
286 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
287 0x068, BIT(13), 0);
289 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
290 0x06c, BIT(0), 0);
291 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
292 0x06c, BIT(1), 0);
293 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
294 0x06c, BIT(2), 0);
295 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
296 0x06c, BIT(16), 0);
297 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
298 0x06c, BIT(17), 0);
299 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
300 0x06c, BIT(18), 0);
301 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
302 0x06c, BIT(19), 0);
303 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
304 0x06c, BIT(20), 0);
306 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
310 24, 2, /* mux */
311 BIT(31), /* gate */
317 24, 2, /* mux */
318 BIT(31), /* gate */
329 24, 2, /* mux */
330 BIT(31), /* gate */
341 24, 2, /* mux */
342 BIT(31), /* gate */
353 24, 2, /* mux */
354 BIT(31), /* gate */
360 24, 2, /* mux */
361 BIT(31), /* gate */
367 24, 2, /* mux */
368 BIT(31), /* gate */
371 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
372 "pll-audio-2x", "pll-audio" };
374 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
377 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
380 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
381 0x0cc, BIT(8), 0);
382 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
383 0x0cc, BIT(9), 0);
384 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
385 0x0cc, BIT(10), 0);
386 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
387 0x0cc, BIT(11), 0);
388 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
389 0x0cc, BIT(16), 0);
391 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr",
394 static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
395 static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents,
398 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
399 0x100, BIT(0), 0);
400 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
401 0x100, BIT(1), 0);
402 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "dram",
403 0x100, BIT(16), 0);
404 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "dram",
405 0x100, BIT(24), 0);
406 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "dram",
407 0x100, BIT(26), 0);
409 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
410 "pll-gpu", "pll-de" };
412 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
414 0x104, 0, 4, 24, 3, BIT(31), 0);
416 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
418 0x10c, 0, 4, 24, 3, BIT(31), 0);
420 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
421 "pll-mipi" };
423 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
425 0x118, 24, 3, BIT(31),
428 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
430 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
432 0x12c, 0, 4, 24, 2, BIT(31), 0);
434 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
435 "pll-mipi", "pll-ve" };
437 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
439 0x134, 16, 4, 24, 3, BIT(31), 0);
441 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
444 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
446 0x134, 0, 5, 8, 3, BIT(15), 0);
448 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
449 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
451 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
452 0x140, BIT(31), CLK_SET_RATE_PARENT);
453 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
454 0x140, BIT(30), CLK_SET_RATE_PARENT);
456 0x144, BIT(31), 0);
458 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
459 "pll-ddr0", "pll-ddr1" };
461 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
463 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
465 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
467 0x168, 16, 4, 24, 2, BIT(31), 0);
469 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
471 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
473 0x168, 0, 4, 8, 2, BIT(15), 0);
477 0x180, 0, 4, 24, 3, BIT(31), 0);
479 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
480 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
482 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
484 0x1b0, 0, 3, 24, 2, BIT(31), 0);
589 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
592 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
595 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
598 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
601 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
604 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
716 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
717 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
718 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
720 [RST_MBUS] = { 0x0fc, BIT(31) },
722 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
723 [RST_BUS_SS] = { 0x2c0, BIT(5) },
724 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
725 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
726 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
727 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
728 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
729 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
730 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
731 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
732 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
733 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
734 [RST_BUS_EHCI] = { 0x2c0, BIT(26) },
735 [RST_BUS_OHCI] = { 0x2c0, BIT(29) },
737 [RST_BUS_VE] = { 0x2c4, BIT(0) },
738 [RST_BUS_LCD] = { 0x2c4, BIT(4) },
739 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
740 [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
741 [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
742 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
743 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
744 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
745 [RST_BUS_DRC] = { 0x2c4, BIT(25) },
746 [RST_BUS_SAT] = { 0x2c4, BIT(26) },
748 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
750 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
751 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
752 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
754 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
755 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
756 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
757 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
758 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
759 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
760 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
761 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
777 .enable = BIT(31),
778 .lock = BIT(28),
784 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
785 .bypass_index = 1, /* index of 24 MHz oscillator */
798 /* Force the PLL-Audio-1x divider to 1 */ in sun8i_a33_ccu_probe()
803 /* Force PLL-MIPI to MIPI mode */ in sun8i_a33_ccu_probe()
805 val &= ~BIT(16); in sun8i_a33_ccu_probe()
808 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a33_ccu_desc); in sun8i_a33_ccu_probe()
823 { .compatible = "allwinner,sun8i-a33-ccu" },
830 .name = "sun8i-a33-ccu",