Lines Matching +full:24 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
30 #include "ccu-sun6i-a31.h"
32 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
37 BIT(31), /* gate */
38 BIT(28), /* lock */
46 * With sigma-delta modulation for fractional-N on the audio PLL,
60 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
64 pll_audio_sdm_table, BIT(24),
65 0x284, BIT(31),
66 BIT(31), /* gate */
67 BIT(28), /* lock */
70 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
74 BIT(24), /* frac enable */
75 BIT(25), /* frac select */
78 BIT(31), /* gate */
79 BIT(28), /* lock */
82 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
86 BIT(24), /* frac enable */
87 BIT(25), /* frac select */
90 BIT(31), /* gate */
91 BIT(28), /* lock */
94 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
99 BIT(31), /* gate */
100 BIT(28), /* lock */
103 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
107 BIT(31), /* gate */
108 BIT(28), /* lock */
109 2, /* post-div */
112 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
116 BIT(24), /* frac enable */
117 BIT(25), /* frac select */
120 BIT(31), /* gate */
121 BIT(28), /* lock */
124 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
128 BIT(24), /* frac enable */
129 BIT(25), /* frac select */
132 BIT(31), /* gate */
133 BIT(28), /* lock */
139 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
145 static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" };
146 static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
152 BIT(31) | BIT(23) | BIT(22), /* gate */
153 BIT(28), /* lock */
160 BIT(24), /* frac enable */
161 BIT(25), /* frac select */
164 BIT(31), /* gate */
165 BIT(28), /* lock */
172 BIT(24), /* frac enable */
173 BIT(25), /* frac select */
176 BIT(31), /* gate */
177 BIT(28), /* lock */
181 "pll-cpu", "pll-cpu" };
203 "axi", "pll-periph" };
241 "pll-periph", "pll-periph" };
245 24, 2, /* mux */
248 static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
249 0x060, BIT(1), 0);
250 static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
251 0x060, BIT(5), 0);
252 static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
253 0x060, BIT(6), 0);
254 static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
255 0x060, BIT(8), 0);
256 static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
257 0x060, BIT(9), 0);
258 static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
259 0x060, BIT(10), 0);
260 static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
261 0x060, BIT(11), 0);
262 static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
263 0x060, BIT(12), 0);
264 static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
265 0x060, BIT(13), 0);
266 static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
267 0x060, BIT(14), 0);
268 static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1",
269 0x060, BIT(17), 0);
270 static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1",
271 0x060, BIT(18), 0);
272 static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1",
273 0x060, BIT(19), 0);
274 static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1",
275 0x060, BIT(20), 0);
276 static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1",
277 0x060, BIT(21), 0);
278 static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1",
279 0x060, BIT(22), 0);
280 static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1",
281 0x060, BIT(23), 0);
282 static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1",
283 0x060, BIT(24), 0);
284 static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1",
285 0x060, BIT(26), 0);
286 static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1",
287 0x060, BIT(27), 0);
288 static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1",
289 0x060, BIT(29), 0);
290 static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1",
291 0x060, BIT(30), 0);
292 static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1",
293 0x060, BIT(31), 0);
295 static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1",
296 0x064, BIT(0), 0);
297 static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1",
298 0x064, BIT(4), 0);
299 static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1",
300 0x064, BIT(5), 0);
301 static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1",
302 0x064, BIT(8), 0);
303 static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1",
304 0x064, BIT(11), 0);
305 static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1",
306 0x064, BIT(12), 0);
307 static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1",
308 0x064, BIT(13), 0);
309 static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1",
310 0x064, BIT(14), 0);
311 static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1",
312 0x064, BIT(15), 0);
313 static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1",
314 0x064, BIT(18), 0);
315 static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1",
316 0x064, BIT(20), 0);
317 static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1",
318 0x064, BIT(23), 0);
319 static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1",
320 0x064, BIT(24), 0);
321 static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1",
322 0x064, BIT(25), 0);
323 static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1",
324 0x064, BIT(26), 0);
326 static SUNXI_CCU_GATE(apb1_codec_clk, "apb1-codec", "apb1",
327 0x068, BIT(0), 0);
328 static SUNXI_CCU_GATE(apb1_spdif_clk, "apb1-spdif", "apb1",
329 0x068, BIT(1), 0);
330 static SUNXI_CCU_GATE(apb1_digital_mic_clk, "apb1-digital-mic", "apb1",
331 0x068, BIT(4), 0);
332 static SUNXI_CCU_GATE(apb1_pio_clk, "apb1-pio", "apb1",
333 0x068, BIT(5), 0);
334 static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1",
335 0x068, BIT(12), 0);
336 static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1",
337 0x068, BIT(13), 0);
339 static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2",
340 0x06c, BIT(0), 0);
341 static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2",
342 0x06c, BIT(1), 0);
343 static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2",
344 0x06c, BIT(2), 0);
345 static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2",
346 0x06c, BIT(3), 0);
347 static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2",
348 0x06c, BIT(16), 0);
349 static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2",
350 0x06c, BIT(17), 0);
351 static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2",
352 0x06c, BIT(18), 0);
353 static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2",
354 0x06c, BIT(19), 0);
355 static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2",
356 0x06c, BIT(20), 0);
357 static SUNXI_CCU_GATE(apb2_uart5_clk, "apb2-uart5", "apb2",
358 0x06c, BIT(21), 0);
360 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
365 24, 2, /* mux */
366 BIT(31), /* gate */
373 24, 2, /* mux */
374 BIT(31), /* gate */
381 24, 2, /* mux */
382 BIT(31), /* gate */
394 24, 2, /* mux */
395 BIT(31), /* gate */
407 24, 2, /* mux */
408 BIT(31), /* gate */
420 24, 2, /* mux */
421 BIT(31), /* gate */
432 24, 2, /* mux */
433 BIT(31), /* gate */
439 24, 2, /* mux */
440 BIT(31), /* gate */
446 24, 2, /* mux */
447 BIT(31), /* gate */
453 24, 2, /* mux */
454 BIT(31), /* gate */
459 24, 2, /* mux */
460 BIT(31), /* gate */
466 24, 2, /* mux */
467 BIT(31), /* gate */
470 static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x",
471 "pll-audio-2x", "pll-audio" };
473 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
475 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
478 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
480 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
481 0x0cc, BIT(8), 0);
482 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
483 0x0cc, BIT(9), 0);
484 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
485 0x0cc, BIT(10), 0);
486 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
487 0x0cc, BIT(16), 0);
488 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
489 0x0cc, BIT(17), 0);
490 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
491 0x0cc, BIT(18), 0);
495 static const char * const dram_parents[] = { "pll-ddr", "pll-periph" };
499 24, 2, /* mux */
500 BIT(31), /* gate */
508 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "mdfs",
509 0x100, BIT(0), 0);
510 static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs",
511 0x100, BIT(1), 0);
512 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "mdfs",
513 0x100, BIT(3), 0);
514 static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "mdfs",
515 0x100, BIT(16), 0);
516 static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "mdfs",
517 0x100, BIT(17), 0);
518 static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "mdfs",
519 0x100, BIT(18), 0);
520 static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "mdfs",
521 0x100, BIT(19), 0);
522 static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "mdfs",
523 0x100, BIT(24), 0);
524 static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "mdfs",
525 0x100, BIT(25), 0);
526 static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "mdfs",
527 0x100, BIT(26), 0);
528 static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "mdfs",
529 0x100, BIT(27), 0);
530 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "mdfs",
531 0x100, BIT(28), 0);
533 static const char * const de_parents[] = { "pll-video0", "pll-video1",
534 "pll-periph-2x", "pll-gpu",
537 0x104, 0, 4, 24, 3, BIT(31), 0);
539 0x108, 0, 4, 24, 3, BIT(31), 0);
541 0x10c, 0, 4, 24, 3, BIT(31), 0);
543 0x110, 0, 4, 24, 3, BIT(31), 0);
545 static const char * const mp_parents[] = { "pll-video0", "pll-video1",
548 0x114, 0, 4, 24, 3, BIT(31), 0);
550 static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1",
551 "pll-video0-2x",
552 "pll-video1-2x", "pll-mipi" };
553 static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents,
554 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
555 static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents,
556 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
558 static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1",
559 "pll-video0-2x",
560 "pll-video1-2x" };
561 static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
562 0x12c, 0, 4, 24, 3, BIT(31),
564 static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
565 0x130, 0, 4, 24, 3, BIT(31),
568 static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
569 "pll9", "pll10", "pll-mipi",
570 "pll-ve" };
571 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents,
572 0x134, 16, 4, 24, 3, BIT(31), 0);
574 static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1",
578 .enable = BIT(15),
583 .hw.init = CLK_HW_INIT_PARENTS("csi0-mclk",
591 .enable = BIT(15),
596 .hw.init = CLK_HW_INIT_PARENTS("csi1-mclk",
603 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
604 0x13c, 16, 3, BIT(31), 0);
606 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
607 0x140, BIT(31), CLK_SET_RATE_PARENT);
609 0x144, BIT(31), 0);
610 static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio",
611 0x148, BIT(31), CLK_SET_RATE_PARENT);
614 0x150, 0, 4, 24, 2, BIT(31),
617 static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0);
619 static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
621 static const char * const mbus_parents[] = { "osc24M", "pll-periph",
622 "pll-ddr" };
626 24, 2, /* mux */
627 BIT(31), /* gate */
633 24, 2, /* mux */
634 BIT(31), /* gate */
637 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents,
638 0x168, 16, 3, 24, 2, BIT(31),
640 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy",
642 BIT(15), CLK_SET_RATE_PARENT);
643 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy",
645 BIT(15), 0);
647 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents,
648 0x180, 0, 3, 24, 2, BIT(31), 0);
649 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents,
650 0x184, 0, 3, 24, 2, BIT(31), 0);
651 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents,
652 0x188, 0, 3, 24, 2, BIT(31), 0);
653 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents,
654 0x18c, 0, 3, 24, 2, BIT(31), 0);
656 static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x",
657 "pll-video0", "pll-video1",
664 .enable = BIT(31),
667 .shift = 24,
675 .hw.init = CLK_HW_INIT_PARENTS("gpu-core",
683 .enable = BIT(31),
686 .shift = 24,
694 .hw.init = CLK_HW_INIT_PARENTS("gpu-memory",
702 .enable = BIT(31),
705 .shift = 24,
713 .hw.init = CLK_HW_INIT_PARENTS("gpu-hyd",
722 24, 2, /* mux */
723 BIT(31), /* gate */
729 24, 2, /* mux */
730 BIT(31), /* gate */
744 .enable = BIT(31),
748 .shift = 24,
757 .hw.init = CLK_HW_INIT_PARENTS("out-a",
765 .enable = BIT(31),
769 .shift = 24,
778 .hw.init = CLK_HW_INIT_PARENTS("out-b",
786 .enable = BIT(31),
790 .shift = 24,
799 .hw.init = CLK_HW_INIT_PARENTS("out-c",
964 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
967 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
970 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
973 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
976 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
979 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
982 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
1150 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1151 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1152 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1154 [RST_AHB1_MIPI_DSI] = { 0x2c0, BIT(1) },
1155 [RST_AHB1_SS] = { 0x2c0, BIT(5) },
1156 [RST_AHB1_DMA] = { 0x2c0, BIT(6) },
1157 [RST_AHB1_MMC0] = { 0x2c0, BIT(8) },
1158 [RST_AHB1_MMC1] = { 0x2c0, BIT(9) },
1159 [RST_AHB1_MMC2] = { 0x2c0, BIT(10) },
1160 [RST_AHB1_MMC3] = { 0x2c0, BIT(11) },
1161 [RST_AHB1_NAND1] = { 0x2c0, BIT(12) },
1162 [RST_AHB1_NAND0] = { 0x2c0, BIT(13) },
1163 [RST_AHB1_SDRAM] = { 0x2c0, BIT(14) },
1164 [RST_AHB1_EMAC] = { 0x2c0, BIT(17) },
1165 [RST_AHB1_TS] = { 0x2c0, BIT(18) },
1166 [RST_AHB1_HSTIMER] = { 0x2c0, BIT(19) },
1167 [RST_AHB1_SPI0] = { 0x2c0, BIT(20) },
1168 [RST_AHB1_SPI1] = { 0x2c0, BIT(21) },
1169 [RST_AHB1_SPI2] = { 0x2c0, BIT(22) },
1170 [RST_AHB1_SPI3] = { 0x2c0, BIT(23) },
1171 [RST_AHB1_OTG] = { 0x2c0, BIT(24) },
1172 [RST_AHB1_EHCI0] = { 0x2c0, BIT(26) },
1173 [RST_AHB1_EHCI1] = { 0x2c0, BIT(27) },
1174 [RST_AHB1_OHCI0] = { 0x2c0, BIT(29) },
1175 [RST_AHB1_OHCI1] = { 0x2c0, BIT(30) },
1176 [RST_AHB1_OHCI2] = { 0x2c0, BIT(31) },
1178 [RST_AHB1_VE] = { 0x2c4, BIT(0) },
1179 [RST_AHB1_LCD0] = { 0x2c4, BIT(4) },
1180 [RST_AHB1_LCD1] = { 0x2c4, BIT(5) },
1181 [RST_AHB1_CSI] = { 0x2c4, BIT(8) },
1182 [RST_AHB1_HDMI] = { 0x2c4, BIT(11) },
1183 [RST_AHB1_BE0] = { 0x2c4, BIT(12) },
1184 [RST_AHB1_BE1] = { 0x2c4, BIT(13) },
1185 [RST_AHB1_FE0] = { 0x2c4, BIT(14) },
1186 [RST_AHB1_FE1] = { 0x2c4, BIT(15) },
1187 [RST_AHB1_MP] = { 0x2c4, BIT(18) },
1188 [RST_AHB1_GPU] = { 0x2c4, BIT(20) },
1189 [RST_AHB1_DEU0] = { 0x2c4, BIT(23) },
1190 [RST_AHB1_DEU1] = { 0x2c4, BIT(24) },
1191 [RST_AHB1_DRC0] = { 0x2c4, BIT(25) },
1192 [RST_AHB1_DRC1] = { 0x2c4, BIT(26) },
1193 [RST_AHB1_LVDS] = { 0x2c8, BIT(0) },
1195 [RST_APB1_CODEC] = { 0x2d0, BIT(0) },
1196 [RST_APB1_SPDIF] = { 0x2d0, BIT(1) },
1197 [RST_APB1_DIGITAL_MIC] = { 0x2d0, BIT(4) },
1198 [RST_APB1_DAUDIO0] = { 0x2d0, BIT(12) },
1199 [RST_APB1_DAUDIO1] = { 0x2d0, BIT(13) },
1201 [RST_APB2_I2C0] = { 0x2d8, BIT(0) },
1202 [RST_APB2_I2C1] = { 0x2d8, BIT(1) },
1203 [RST_APB2_I2C2] = { 0x2d8, BIT(2) },
1204 [RST_APB2_I2C3] = { 0x2d8, BIT(3) },
1205 [RST_APB2_UART0] = { 0x2d8, BIT(16) },
1206 [RST_APB2_UART1] = { 0x2d8, BIT(17) },
1207 [RST_APB2_UART2] = { 0x2d8, BIT(18) },
1208 [RST_APB2_UART3] = { 0x2d8, BIT(19) },
1209 [RST_APB2_UART4] = { 0x2d8, BIT(20) },
1210 [RST_APB2_UART5] = { 0x2d8, BIT(21) },
1226 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
1227 .bypass_index = 1, /* index of 24 MHz oscillator */
1240 /* Force the PLL-Audio-1x divider to 1 */ in sun6i_a31_ccu_probe()
1245 /* Force PLL-MIPI to MIPI mode */ in sun6i_a31_ccu_probe()
1247 val &= BIT(16); in sun6i_a31_ccu_probe()
1252 /* set PLL6 pre-div = 3 */ in sun6i_a31_ccu_probe()
1255 /* select PLL6 / pre-div */ in sun6i_a31_ccu_probe()
1260 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun6i_a31_ccu_desc); in sun6i_a31_ccu_probe()
1271 { .compatible = "allwinner,sun6i-a31-ccu" },
1278 .name = "sun6i-a31-ccu",