Lines Matching +full:0 +full:x2c4
33 "osc24M", 0x000,
36 0, 2, /* M */
39 0);
53 #define SUN6I_A31_PLL_AUDIO_REG 0x008
56 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
57 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
61 "osc24M", 0x008,
63 0, 5, /* M */
65 0x284, BIT(31),
71 "osc24M", 0x010,
73 0, 4, /* M */
76 270000000, /* frac rate 0 */
83 "osc24M", 0x018,
85 0, 4, /* M */
88 270000000, /* frac rate 0 */
95 "osc24M", 0x020,
98 0, 2, /* M */
104 "osc24M", 0x028,
113 "osc24M", 0x030,
115 0, 4, /* M */
118 270000000, /* frac rate 0 */
125 "osc24M", 0x038,
127 0, 4, /* M */
130 270000000, /* frac rate 0 */
143 #define SUN6I_A31_PLL_MIPI_REG 0x040
147 pll_mipi_parents, 0x040,
150 0, 4, /* M */
151 21, 0, /* mux */
157 "osc24M", 0x044,
159 0, 4, /* M */
162 270000000, /* frac rate 0 */
169 "osc24M", 0x048,
171 0, 4, /* M */
174 270000000, /* frac rate 0 */
183 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
186 { .val = 0, .div = 1 },
198 0x050, 0, 3, axi_div_table, 0);
200 #define SUN6I_A31_AHB1_REG 0x054
220 .reg = 0x054,
225 0),
230 { .val = 0, .div = 2 },
238 0x054, 8, 2, apb1_div_table, 0);
242 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
243 0, 5, /* M */
246 0);
249 0x060, BIT(1), 0);
251 0x060, BIT(5), 0);
253 0x060, BIT(6), 0);
255 0x060, BIT(8), 0);
257 0x060, BIT(9), 0);
259 0x060, BIT(10), 0);
261 0x060, BIT(11), 0);
263 0x060, BIT(12), 0);
265 0x060, BIT(13), 0);
267 0x060, BIT(14), 0);
269 0x060, BIT(17), 0);
271 0x060, BIT(18), 0);
273 0x060, BIT(19), 0);
275 0x060, BIT(20), 0);
277 0x060, BIT(21), 0);
279 0x060, BIT(22), 0);
281 0x060, BIT(23), 0);
283 0x060, BIT(24), 0);
285 0x060, BIT(26), 0);
287 0x060, BIT(27), 0);
289 0x060, BIT(29), 0);
291 0x060, BIT(30), 0);
293 0x060, BIT(31), 0);
296 0x064, BIT(0), 0);
298 0x064, BIT(4), 0);
300 0x064, BIT(5), 0);
302 0x064, BIT(8), 0);
304 0x064, BIT(11), 0);
306 0x064, BIT(12), 0);
308 0x064, BIT(13), 0);
310 0x064, BIT(14), 0);
312 0x064, BIT(15), 0);
314 0x064, BIT(18), 0);
316 0x064, BIT(20), 0);
318 0x064, BIT(23), 0);
320 0x064, BIT(24), 0);
322 0x064, BIT(25), 0);
324 0x064, BIT(26), 0);
327 0x068, BIT(0), 0);
329 0x068, BIT(1), 0);
331 0x068, BIT(4), 0);
333 0x068, BIT(5), 0);
335 0x068, BIT(12), 0);
337 0x068, BIT(13), 0);
340 0x06c, BIT(0), 0);
342 0x06c, BIT(1), 0);
344 0x06c, BIT(2), 0);
346 0x06c, BIT(3), 0);
348 0x06c, BIT(16), 0);
350 0x06c, BIT(17), 0);
352 0x06c, BIT(18), 0);
354 0x06c, BIT(19), 0);
356 0x06c, BIT(20), 0);
358 0x06c, BIT(21), 0);
362 0x080,
363 0, 4, /* M */
367 0);
370 0x084,
371 0, 4, /* M */
375 0);
378 0x088,
379 0, 4, /* M */
383 0);
386 0x088, 20, 3, 0);
388 0x088, 8, 3, 0);
391 0x08c,
392 0, 4, /* M */
396 0);
399 0x08c, 20, 3, 0);
401 0x08c, 8, 3, 0);
404 0x090,
405 0, 4, /* M */
409 0);
412 0x090, 20, 3, 0);
414 0x090, 8, 3, 0);
417 0x094,
418 0, 4, /* M */
422 0);
425 0x094, 20, 3, 0);
427 0x094, 8, 3, 0);
429 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
430 0, 4, /* M */
434 0);
436 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
437 0, 4, /* M */
441 0);
443 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
444 0, 4, /* M */
448 0);
450 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
451 0, 4, /* M */
455 0);
456 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
457 0, 4, /* M */
461 0);
463 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
464 0, 4, /* M */
468 0);
473 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
475 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
478 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
481 0x0cc, BIT(8), 0);
483 0x0cc, BIT(9), 0);
485 0x0cc, BIT(10), 0);
487 0x0cc, BIT(16), 0);
489 0x0cc, BIT(17), 0);
491 0x0cc, BIT(18), 0);
496 static SUNXI_CCU_MP_WITH_MUX_GATE(mdfs_clk, "mdfs", dram_parents, 0x0f0,
497 0, 4, /* M */
504 0x0f4, 0, 4, 4, 1, CLK_IS_CRITICAL);
506 0x0f4, 8, 4, 12, 1, CLK_IS_CRITICAL);
509 0x100, BIT(0), 0);
511 0x100, BIT(1), 0);
513 0x100, BIT(3), 0);
515 0x100, BIT(16), 0);
517 0x100, BIT(17), 0);
519 0x100, BIT(18), 0);
521 0x100, BIT(19), 0);
523 0x100, BIT(24), 0);
525 0x100, BIT(25), 0);
527 0x100, BIT(26), 0);
529 0x100, BIT(27), 0);
531 0x100, BIT(28), 0);
537 0x104, 0, 4, 24, 3, BIT(31), 0);
539 0x108, 0, 4, 24, 3, BIT(31), 0);
541 0x10c, 0, 4, 24, 3, BIT(31), 0);
543 0x110, 0, 4, 24, 3, BIT(31), 0);
548 0x114, 0, 4, 24, 3, BIT(31), 0);
554 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
556 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
562 0x12c, 0, 4, 24, 3, BIT(31),
565 0x130, 0, 4, 24, 3, BIT(31),
572 0x134, 16, 4, 24, 3, BIT(31), 0);
576 static const u8 csi_mclk_table[] = { 0, 1, 5 };
579 .div = _SUNXI_CCU_DIV(0, 4),
582 .reg = 0x134,
586 0),
592 .div = _SUNXI_CCU_DIV(0, 4),
595 .reg = 0x138,
599 0),
604 0x13c, 16, 3, BIT(31), 0);
607 0x140, BIT(31), CLK_SET_RATE_PARENT);
609 0x144, BIT(31), 0);
611 0x148, BIT(31), CLK_SET_RATE_PARENT);
614 0x150, 0, 4, 24, 2, BIT(31),
617 static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0);
619 static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
623 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus0_clk, "mbus0", mbus_parents, 0x15c,
624 0, 3, /* M */
630 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus1_clk, "mbus1", mbus_parents, 0x160,
631 0, 3, /* M */
638 0x168, 16, 3, 24, 2, BIT(31),
641 lcd_ch1_parents, 0x168, 0, 3, 8, 2,
644 lcd_ch1_parents, 0x16c, 0, 3, 8, 2,
645 BIT(15), 0);
648 0x180, 0, 3, 24, 2, BIT(31), 0);
650 0x184, 0, 3, 24, 2, BIT(31), 0);
652 0x188, 0, 3, 24, 2, BIT(31), 0);
654 0x18c, 0, 3, 24, 2, BIT(31), 0);
665 .div = _SUNXI_CCU_DIV(0, 3),
673 .reg = 0x1a0,
678 0),
684 .div = _SUNXI_CCU_DIV(0, 3),
692 .reg = 0x1a4,
697 0),
703 .div = _SUNXI_CCU_DIV(0, 3),
711 .reg = 0x1a8,
716 0),
720 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", mod0_default_parents, 0x1b0,
721 0, 3, /* M */
724 0);
727 0x1b0,
728 0, 3, /* M */
731 0);
735 static const u8 clk_out_table[] = { 0, 1, 2, 11, 13 };
738 { .index = 0, .div = 750, },
755 .reg = 0x300,
760 0),
776 .reg = 0x304,
781 0),
797 .reg = 0x308,
802 0),
978 1, 2, 0);
1150 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1151 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1152 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1154 [RST_AHB1_MIPI_DSI] = { 0x2c0, BIT(1) },
1155 [RST_AHB1_SS] = { 0x2c0, BIT(5) },
1156 [RST_AHB1_DMA] = { 0x2c0, BIT(6) },
1157 [RST_AHB1_MMC0] = { 0x2c0, BIT(8) },
1158 [RST_AHB1_MMC1] = { 0x2c0, BIT(9) },
1159 [RST_AHB1_MMC2] = { 0x2c0, BIT(10) },
1160 [RST_AHB1_MMC3] = { 0x2c0, BIT(11) },
1161 [RST_AHB1_NAND1] = { 0x2c0, BIT(12) },
1162 [RST_AHB1_NAND0] = { 0x2c0, BIT(13) },
1163 [RST_AHB1_SDRAM] = { 0x2c0, BIT(14) },
1164 [RST_AHB1_EMAC] = { 0x2c0, BIT(17) },
1165 [RST_AHB1_TS] = { 0x2c0, BIT(18) },
1166 [RST_AHB1_HSTIMER] = { 0x2c0, BIT(19) },
1167 [RST_AHB1_SPI0] = { 0x2c0, BIT(20) },
1168 [RST_AHB1_SPI1] = { 0x2c0, BIT(21) },
1169 [RST_AHB1_SPI2] = { 0x2c0, BIT(22) },
1170 [RST_AHB1_SPI3] = { 0x2c0, BIT(23) },
1171 [RST_AHB1_OTG] = { 0x2c0, BIT(24) },
1172 [RST_AHB1_EHCI0] = { 0x2c0, BIT(26) },
1173 [RST_AHB1_EHCI1] = { 0x2c0, BIT(27) },
1174 [RST_AHB1_OHCI0] = { 0x2c0, BIT(29) },
1175 [RST_AHB1_OHCI1] = { 0x2c0, BIT(30) },
1176 [RST_AHB1_OHCI2] = { 0x2c0, BIT(31) },
1178 [RST_AHB1_VE] = { 0x2c4, BIT(0) },
1179 [RST_AHB1_LCD0] = { 0x2c4, BIT(4) },
1180 [RST_AHB1_LCD1] = { 0x2c4, BIT(5) },
1181 [RST_AHB1_CSI] = { 0x2c4, BIT(8) },
1182 [RST_AHB1_HDMI] = { 0x2c4, BIT(11) },
1183 [RST_AHB1_BE0] = { 0x2c4, BIT(12) },
1184 [RST_AHB1_BE1] = { 0x2c4, BIT(13) },
1185 [RST_AHB1_FE0] = { 0x2c4, BIT(14) },
1186 [RST_AHB1_FE1] = { 0x2c4, BIT(15) },
1187 [RST_AHB1_MP] = { 0x2c4, BIT(18) },
1188 [RST_AHB1_GPU] = { 0x2c4, BIT(20) },
1189 [RST_AHB1_DEU0] = { 0x2c4, BIT(23) },
1190 [RST_AHB1_DEU1] = { 0x2c4, BIT(24) },
1191 [RST_AHB1_DRC0] = { 0x2c4, BIT(25) },
1192 [RST_AHB1_DRC1] = { 0x2c4, BIT(26) },
1193 [RST_AHB1_LVDS] = { 0x2c8, BIT(0) },
1195 [RST_APB1_CODEC] = { 0x2d0, BIT(0) },
1196 [RST_APB1_SPDIF] = { 0x2d0, BIT(1) },
1197 [RST_APB1_DIGITAL_MIC] = { 0x2d0, BIT(4) },
1198 [RST_APB1_DAUDIO0] = { 0x2d0, BIT(12) },
1199 [RST_APB1_DAUDIO1] = { 0x2d0, BIT(13) },
1201 [RST_APB2_I2C0] = { 0x2d8, BIT(0) },
1202 [RST_APB2_I2C1] = { 0x2d8, BIT(1) },
1203 [RST_APB2_I2C2] = { 0x2d8, BIT(2) },
1204 [RST_APB2_I2C3] = { 0x2d8, BIT(3) },
1205 [RST_APB2_UART0] = { 0x2d8, BIT(16) },
1206 [RST_APB2_UART1] = { 0x2d8, BIT(17) },
1207 [RST_APB2_UART2] = { 0x2d8, BIT(18) },
1208 [RST_APB2_UART3] = { 0x2d8, BIT(19) },
1209 [RST_APB2_UART4] = { 0x2d8, BIT(20) },
1210 [RST_APB2_UART5] = { 0x2d8, BIT(21) },
1236 reg = devm_platform_ioremap_resource(pdev, 0); in sun6i_a31_ccu_probe()
1243 writel(val | (0 << 16), reg + SUN6I_A31_PLL_AUDIO_REG); in sun6i_a31_ccu_probe()
1254 val |= 0x2 << 6; in sun6i_a31_ccu_probe()
1257 val |= 0x3 << 12; in sun6i_a31_ccu_probe()
1267 return 0; in sun6i_a31_ccu_probe()