clk/sunxi-ng/ccu-sun50i-a64.c

1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun50i-a64.h"
35 		.hw.init	= CLK_HW_INIT("pll-cpux",
47  * With sigma-delta modulation for fractional-N on the audio PLL,
61 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
71 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(pll_video0_clk, "pll-video0",
85 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
97 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
115 		.hw.init	= CLK_HW_INIT("pll-periph0", "osc24M",
129 		.hw.init	= CLK_HW_INIT("pll-periph1", "osc24M",
134 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
148 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
181 		.hw.init	= CLK_HW_INIT("pll-mipi", "pll-video0",
190 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
202 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
214 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
223 					     "pll-cpux", "pll-cpux" };
230 					     "axi", "pll-periph0" };
266 					     "pll-periph0-2x",
267 					     "pll-periph0-2x" };
274 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
296 static SUNXI_CCU_GATE(bus_mipi_dsi_clk,	"bus-mipi-dsi",	"ahb1",
298 static SUNXI_CCU_GATE(bus_ce_clk,	"bus-ce",	"ahb1",
300 static SUNXI_CCU_GATE(bus_dma_clk,	"bus-dma",	"ahb1",
302 static SUNXI_CCU_GATE(bus_mmc0_clk,	"bus-mmc0",	"ahb1",
304 static SUNXI_CCU_GATE(bus_mmc1_clk,	"bus-mmc1",	"ahb1",
306 static SUNXI_CCU_GATE(bus_mmc2_clk,	"bus-mmc2",	"ahb1",
308 static SUNXI_CCU_GATE(bus_nand_clk,	"bus-nand",	"ahb1",
310 static SUNXI_CCU_GATE(bus_dram_clk,	"bus-dram",	"ahb1",
312 static SUNXI_CCU_GATE(bus_emac_clk,	"bus-emac",	"ahb2",
314 static SUNXI_CCU_GATE(bus_ts_clk,	"bus-ts",	"ahb1",
316 static SUNXI_CCU_GATE(bus_hstimer_clk,	"bus-hstimer",	"ahb1",
318 static SUNXI_CCU_GATE(bus_spi0_clk,	"bus-spi0",	"ahb1",
320 static SUNXI_CCU_GATE(bus_spi1_clk,	"bus-spi1",	"ahb1",
322 static SUNXI_CCU_GATE(bus_otg_clk,	"bus-otg",	"ahb1",
324 static SUNXI_CCU_GATE(bus_ehci0_clk,	"bus-ehci0",	"ahb1",
326 static SUNXI_CCU_GATE(bus_ehci1_clk,	"bus-ehci1",	"ahb2",
328 static SUNXI_CCU_GATE(bus_ohci0_clk,	"bus-ohci0",	"ahb1",
330 static SUNXI_CCU_GATE(bus_ohci1_clk,	"bus-ohci1",	"ahb2",
333 static SUNXI_CCU_GATE(bus_ve_clk,	"bus-ve",	"ahb1",
335 static SUNXI_CCU_GATE(bus_tcon0_clk,	"bus-tcon0",	"ahb1",
337 static SUNXI_CCU_GATE(bus_tcon1_clk,	"bus-tcon1",	"ahb1",
339 static SUNXI_CCU_GATE(bus_deinterlace_clk,	"bus-deinterlace",	"ahb1",
341 static SUNXI_CCU_GATE(bus_csi_clk,	"bus-csi",	"ahb1",
343 static SUNXI_CCU_GATE(bus_hdmi_clk,	"bus-hdmi",	"ahb1",
345 static SUNXI_CCU_GATE(bus_de_clk,	"bus-de",	"ahb1",
347 static SUNXI_CCU_GATE(bus_gpu_clk,	"bus-gpu",	"ahb1",
349 static SUNXI_CCU_GATE(bus_msgbox_clk,	"bus-msgbox",	"ahb1",
351 static SUNXI_CCU_GATE(bus_spinlock_clk,	"bus-spinlock",	"ahb1",
354 static SUNXI_CCU_GATE(bus_codec_clk,	"bus-codec",	"apb1",
356 static SUNXI_CCU_GATE(bus_spdif_clk,	"bus-spdif",	"apb1",
358 static SUNXI_CCU_GATE(bus_pio_clk,	"bus-pio",	"apb1",
360 static SUNXI_CCU_GATE(bus_ths_clk,	"bus-ths",	"apb1",
362 static SUNXI_CCU_GATE(bus_i2s0_clk,	"bus-i2s0",	"apb1",
364 static SUNXI_CCU_GATE(bus_i2s1_clk,	"bus-i2s1",	"apb1",
366 static SUNXI_CCU_GATE(bus_i2s2_clk,	"bus-i2s2",	"apb1",
369 static SUNXI_CCU_GATE(bus_i2c0_clk,	"bus-i2c0",	"apb2",
371 static SUNXI_CCU_GATE(bus_i2c1_clk,	"bus-i2c1",	"apb2",
373 static SUNXI_CCU_GATE(bus_i2c2_clk,	"bus-i2c2",	"apb2",
375 static SUNXI_CCU_GATE(bus_scr_clk,	"bus-scr",	"apb2",
377 static SUNXI_CCU_GATE(bus_uart0_clk,	"bus-uart0",	"apb2",
379 static SUNXI_CCU_GATE(bus_uart1_clk,	"bus-uart1",	"apb2",
381 static SUNXI_CCU_GATE(bus_uart2_clk,	"bus-uart2",	"apb2",
383 static SUNXI_CCU_GATE(bus_uart3_clk,	"bus-uart3",	"apb2",
385 static SUNXI_CCU_GATE(bus_uart4_clk,	"bus-uart4",	"apb2",
388 static SUNXI_CCU_GATE(bus_dbg_clk,	"bus-dbg",	"ahb1",
412 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
413 						     "pll-periph1" };
430  * module clock in the MMC driver, just for the A64.
432 static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
433 						    "pll-periph1-2x" };
440 					  2,		/* post-div */
449 					  2,		/* post-div */
458 					  2,		/* post-div */
461 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
490 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
491 					    "pll-audio-2x", "pll-audio" };
501 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
504 static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
506 static SUNXI_CCU_GATE(usb_phy1_clk,	"usb-phy1",	"osc24M",
508 static SUNXI_CCU_GATE(usb_hsic_clk,	"usb-hsic",	"pll-hsic",
510 static SUNXI_CCU_GATE(usb_hsic_12m_clk,	"usb-hsic-12M",	"osc12M",
512 static SUNXI_CCU_GATE(usb_ohci0_clk,	"usb-ohci0",	"osc12M",
514 static SUNXI_CCU_GATE(usb_ohci1_clk,	"usb-ohci1",	"usb-ohci0",
517 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
521 static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"dram",
523 static SUNXI_CCU_GATE(dram_csi_clk,	"dram-csi",	"dram",
525 static SUNXI_CCU_GATE(dram_deinterlace_clk,	"dram-deinterlace",	"dram",
527 static SUNXI_CCU_GATE(dram_ts_clk,	"dram-ts",	"dram",
530 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
541 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
547 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
556 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
560 static SUNXI_CCU_GATE(csi_misc_clk,	"csi-misc",	"osc24M",
563 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
564 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
567 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
568 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
571 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
574 static SUNXI_CCU_GATE(ac_dig_clk,	"ac-dig",	"pll-audio",
577 static SUNXI_CCU_GATE(ac_dig_4x_clk,	"ac-dig-4x",	"pll-audio-4x",
583 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
587 static SUNXI_CCU_GATE(hdmi_ddc_clk,	"hdmi-ddc",	"osc24M",
590 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
591 						 "pll-ddr0", "pll-ddr1" };
595 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
597 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(dsi_dphy_clk, "dsi-dphy",
601 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
612 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
615 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
618 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
621 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
624 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
627 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
630 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
953 	/* Force the PLL-Audio-1x divider to 1 */  in sun50i_a64_ccu_probe()
965 	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);  in sun50i_a64_ccu_probe()
980 	{ .compatible = "allwinner,sun50i-a64-ccu" },
987 		.name	= "sun50i-a64-ccu",