1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
8 #include "stratix10-clk.h"
27 	if (socfpgaclk->fixed_div) {  in socfpga_gate_clk_recalc_rate()
28 		div = socfpgaclk->fixed_div;  in socfpga_gate_clk_recalc_rate()
29 	} else if (socfpgaclk->div_reg) {  in socfpga_gate_clk_recalc_rate()
30 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;  in socfpga_gate_clk_recalc_rate()
31 		val &= GENMASK(socfpgaclk->width - 1, 0);  in socfpga_gate_clk_recalc_rate()
43 	val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;  in socfpga_dbg_clk_recalc_rate()
44 	val &= GENMASK(socfpgaclk->width - 1, 0);  in socfpga_dbg_clk_recalc_rate()
58 	if (socfpgaclk->bypass_reg) {  in socfpga_gate_get_parent()
59 		mask = (0x1 << socfpgaclk->bypass_shift);  in socfpga_gate_get_parent()
60 		parent = ((readl(socfpgaclk->bypass_reg) & mask) >>  in socfpga_gate_get_parent()
61 			  socfpgaclk->bypass_shift);  in socfpga_gate_get_parent()
67 		second_bypass = readl(socfpgaclk->bypass_reg -  in socfpga_gate_get_parent()
88 	if (socfpgaclk->bypass_reg) {  in socfpga_agilex_gate_get_parent()
89 		mask = (0x1 << socfpgaclk->bypass_shift);  in socfpga_agilex_gate_get_parent()
90 		parent = ((readl(socfpgaclk->bypass_reg) & mask) >>  in socfpga_agilex_gate_get_parent()
91 			  socfpgaclk->bypass_shift);  in socfpga_agilex_gate_get_parent()
97 		second_bypass = readl(socfpgaclk->bypass_reg -  in socfpga_agilex_gate_get_parent()
131 	struct clk_init_data init;  in s10_register_gate()  local
132 	const char *parent_name = clks->parent_name;  in s10_register_gate()
139 	socfpga_clk->hw.reg = regbase + clks->gate_reg;  in s10_register_gate()
140 	socfpga_clk->hw.bit_idx = clks->gate_idx;  in s10_register_gate()
145 	socfpga_clk->fixed_div = clks->fixed_div;  in s10_register_gate()
147 	if (clks->div_reg)  in s10_register_gate()
148 		socfpga_clk->div_reg = regbase + clks->div_reg;  in s10_register_gate()
150 		socfpga_clk->div_reg = NULL;  in s10_register_gate()
152 	socfpga_clk->width = clks->div_width;  in s10_register_gate()
153 	socfpga_clk->shift = clks->div_offset;  in s10_register_gate()
155 	if (clks->bypass_reg)  in s10_register_gate()
156 		socfpga_clk->bypass_reg = regbase + clks->bypass_reg;  in s10_register_gate()
158 		socfpga_clk->bypass_reg = NULL;  in s10_register_gate()
159 	socfpga_clk->bypass_shift = clks->bypass_shift;  in s10_register_gate()
161 	if (streq(clks->name, "cs_pdbg_clk"))  in s10_register_gate()
162 		init.ops = &dbgclk_ops;  in s10_register_gate()
164 		init.ops = &gateclk_ops;  in s10_register_gate()
166 	init.name = clks->name;  in s10_register_gate()
167 	init.flags = clks->flags;  in s10_register_gate()
169 	init.num_parents = clks->num_parents;  in s10_register_gate()
170 	init.parent_names = parent_name ? &parent_name : NULL;  in s10_register_gate()
171 	if (init.parent_names == NULL)  in s10_register_gate()
172 		init.parent_data = clks->parent_data;  in s10_register_gate()
173 	socfpga_clk->hw.hw.init = &init;  in s10_register_gate()
175 	hw_clk = &socfpga_clk->hw.hw;  in s10_register_gate()
177 	ret = clk_hw_register(NULL, &socfpga_clk->hw.hw);  in s10_register_gate()
189 	struct clk_init_data init;  in agilex_register_gate()  local
190 	const char *parent_name = clks->parent_name;  in agilex_register_gate()
197 	socfpga_clk->hw.reg = regbase + clks->gate_reg;  in agilex_register_gate()
198 	socfpga_clk->hw.bit_idx = clks->gate_idx;  in agilex_register_gate()
203 	socfpga_clk->fixed_div = clks->fixed_div;  in agilex_register_gate()
205 	if (clks->div_reg)  in agilex_register_gate()
206 		socfpga_clk->div_reg = regbase + clks->div_reg;  in agilex_register_gate()
208 		socfpga_clk->div_reg = NULL;  in agilex_register_gate()
210 	socfpga_clk->width = clks->div_width;  in agilex_register_gate()
211 	socfpga_clk->shift = clks->div_offset;  in agilex_register_gate()
213 	if (clks->bypass_reg)  in agilex_register_gate()
214 		socfpga_clk->bypass_reg = regbase + clks->bypass_reg;  in agilex_register_gate()
216 		socfpga_clk->bypass_reg = NULL;  in agilex_register_gate()
217 	socfpga_clk->bypass_shift = clks->bypass_shift;  in agilex_register_gate()
219 	if (streq(clks->name, "cs_pdbg_clk"))  in agilex_register_gate()
220 		init.ops = &dbgclk_ops;  in agilex_register_gate()
222 		init.ops = &agilex_gateclk_ops;  in agilex_register_gate()
224 	init.name = clks->name;  in agilex_register_gate()
225 	init.flags = clks->flags;  in agilex_register_gate()
227 	init.num_parents = clks->num_parents;  in agilex_register_gate()
228 	init.parent_names = parent_name ? &parent_name : NULL;  in agilex_register_gate()
229 	if (init.parent_names == NULL)  in agilex_register_gate()
230 		init.parent_data = clks->parent_data;  in agilex_register_gate()
231 	socfpga_clk->hw.hw.init = &init;  in agilex_register_gate()
233 	hw_clk = &socfpga_clk->hw.hw;  in agilex_register_gate()
235 	ret = clk_hw_register(NULL, &socfpga_clk->hw.hw);  in agilex_register_gate()