20  * @pd: PRCI context
24  * address of the PRCI register target described by @pd, and return
29  * Return: the contents of the register described by @pd and @offs.
31 static u32 __prci_readl(struct __prci_data *pd, u32 offs)  in __prci_readl()  argument
33 	return readl_relaxed(pd->va + offs);  in __prci_readl()
36 static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)  in __prci_writel()  argument
38 	writel_relaxed(v, pd->va + offs);  in __prci_writel()
116  * @pd: PRCI context
120  * the PRCI identified by @pd, and store it into the local configuration
124  *          @pd and @pwd from changing during execution.
126 static void __prci_wrpll_read_cfg0(struct __prci_data *pd,  in __prci_wrpll_read_cfg0()  argument
129 	__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));  in __prci_wrpll_read_cfg0()
134  * @pd: PRCI context
144  *          @pd and @pwd from changing during execution.
146 static void __prci_wrpll_write_cfg0(struct __prci_data *pd,  in __prci_wrpll_write_cfg0()  argument
150 	__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);  in __prci_wrpll_write_cfg0()
158  * @pd: PRCI context
162 static void __prci_wrpll_write_cfg1(struct __prci_data *pd,  in __prci_wrpll_write_cfg1()  argument
166 	__prci_writel(enable, pwd->cfg1_offs, pd);  in __prci_wrpll_write_cfg1()
205 	struct __prci_data *pd = pc->pd;  in sifive_prci_wrpll_set_rate()  local
213 		pwd->enable_bypass(pd);  in sifive_prci_wrpll_set_rate()
215 	__prci_wrpll_write_cfg0(pd, pwd, &pwd->c);  in sifive_prci_wrpll_set_rate()
226 	struct __prci_data *pd = pc->pd;  in sifive_clk_is_enabled()  local
229 	r = __prci_readl(pd, pwd->cfg1_offs);  in sifive_clk_is_enabled()
241 	struct __prci_data *pd = pc->pd;  in sifive_prci_clock_enable()  local
246 	__prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);  in sifive_prci_clock_enable()
249 		pwd->disable_bypass(pd);  in sifive_prci_clock_enable()
258 	struct __prci_data *pd = pc->pd;  in sifive_prci_clock_disable()  local
262 		pwd->enable_bypass(pd);  in sifive_prci_clock_disable()
264 	r = __prci_readl(pd, pwd->cfg1_offs);  in sifive_prci_clock_disable()
267 	__prci_wrpll_write_cfg1(pd, pwd, r);  in sifive_prci_clock_disable()
276 	struct __prci_data *pd = pc->pd;  in sifive_prci_tlclksel_recalc_rate()  local
280 	v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);  in sifive_prci_tlclksel_recalc_rate()
293 	struct __prci_data *pd = pc->pd;  in sifive_prci_hfpclkplldiv_recalc_rate()  local
294 	u32 div = __prci_readl(pd, PRCI_HFPCLKPLLDIV_OFFSET);  in sifive_prci_hfpclkplldiv_recalc_rate()
305  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
312 void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd)  in sifive_prci_coreclksel_use_hfclk()  argument
316 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);  in sifive_prci_coreclksel_use_hfclk()
318 	__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);  in sifive_prci_coreclksel_use_hfclk()
320 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);	/* barrier */  in sifive_prci_coreclksel_use_hfclk()
326  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
333 void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd)  in sifive_prci_coreclksel_use_corepll()  argument
337 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);  in sifive_prci_coreclksel_use_corepll()
339 	__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);  in sifive_prci_coreclksel_use_corepll()
341 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);	/* barrier */  in sifive_prci_coreclksel_use_corepll()
347  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
355 void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd)  in sifive_prci_coreclksel_use_final_corepll()  argument
359 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);  in sifive_prci_coreclksel_use_final_corepll()
361 	__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);  in sifive_prci_coreclksel_use_final_corepll()
363 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);	/* barrier */  in sifive_prci_coreclksel_use_final_corepll()
369  * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
376 void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd)  in sifive_prci_corepllsel_use_dvfscorepll()  argument
380 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);  in sifive_prci_corepllsel_use_dvfscorepll()
382 	__prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);  in sifive_prci_corepllsel_use_dvfscorepll()
384 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);	/* barrier */  in sifive_prci_corepllsel_use_dvfscorepll()
390  * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
397 void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd)  in sifive_prci_corepllsel_use_corepll()  argument
401 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);  in sifive_prci_corepllsel_use_corepll()
403 	__prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);  in sifive_prci_corepllsel_use_corepll()
405 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);	/* barrier */  in sifive_prci_corepllsel_use_corepll()
411  * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
418 void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd)  in sifive_prci_hfpclkpllsel_use_hfclk()  argument
422 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);  in sifive_prci_hfpclkpllsel_use_hfclk()
424 	__prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);  in sifive_prci_hfpclkpllsel_use_hfclk()
426 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);	/* barrier */  in sifive_prci_hfpclkpllsel_use_hfclk()
432  * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
439 void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd)  in sifive_prci_hfpclkpllsel_use_hfpclkpll()  argument
443 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);  in sifive_prci_hfpclkpllsel_use_hfpclkpll()
445 	__prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);  in sifive_prci_hfpclkpllsel_use_hfpclkpll()
447 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);	/* barrier */  in sifive_prci_hfpclkpllsel_use_hfpclkpll()
454 	struct __prci_data *pd = pc->pd;  in sifive_prci_pcie_aux_clock_is_enabled()  local
457 	r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);  in sifive_prci_pcie_aux_clock_is_enabled()
468 	struct __prci_data *pd = pc->pd;  in sifive_prci_pcie_aux_clock_enable()  local
474 	__prci_writel(1, PRCI_PCIE_AUX_OFFSET, pd);  in sifive_prci_pcie_aux_clock_enable()
475 	r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);	/* barrier */  in sifive_prci_pcie_aux_clock_enable()
483 	struct __prci_data *pd = pc->pd;  in sifive_prci_pcie_aux_clock_disable()  local
486 	__prci_writel(0, PRCI_PCIE_AUX_OFFSET, pd);  in sifive_prci_pcie_aux_clock_disable()
487 	r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);	/* barrier */  in sifive_prci_pcie_aux_clock_disable()
494  * @pd: The pointer for PRCI per-device instance data
502 static int __prci_register_clocks(struct device *dev, struct __prci_data *pd,  in __prci_register_clocks()  argument
526 		pic->pd = pd;  in __prci_register_clocks()
529 			__prci_wrpll_read_cfg0(pd, pic->pwd);  in __prci_register_clocks()
538 		pd->hw_clks.hws[i] = &pic->hw;  in __prci_register_clocks()
541 	pd->hw_clks.num = i;  in __prci_register_clocks()
544 					&pd->hw_clks);  in __prci_register_clocks()
562 	struct __prci_data *pd;  in sifive_prci_probe()  local
568 	pd = devm_kzalloc(dev, struct_size(pd, hw_clks.hws, desc->num_clks), GFP_KERNEL);  in sifive_prci_probe()
569 	if (!pd)  in sifive_prci_probe()
572 	pd->va = devm_platform_ioremap_resource(pdev, 0);  in sifive_prci_probe()
573 	if (IS_ERR(pd->va))  in sifive_prci_probe()
574 		return PTR_ERR(pd->va);  in sifive_prci_probe()
576 	pd->reset.rcdev.owner = THIS_MODULE;  in sifive_prci_probe()
577 	pd->reset.rcdev.nr_resets = PRCI_RST_NR;  in sifive_prci_probe()
578 	pd->reset.rcdev.ops = &reset_simple_ops;  in sifive_prci_probe()
579 	pd->reset.rcdev.of_node = pdev->dev.of_node;  in sifive_prci_probe()
580 	pd->reset.active_low = true;  in sifive_prci_probe()
581 	pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;  in sifive_prci_probe()
582 	spin_lock_init(&pd->reset.lock);  in sifive_prci_probe()
584 	r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev);  in sifive_prci_probe()
589 	r = __prci_register_clocks(dev, pd, desc);  in sifive_prci_probe()