Lines Matching refs:HCLK_GATE
31 #define HCLK_GATE 0x030 macro
75 HCLK_GATE,
197 GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29),
198 GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28),
199 GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27),
200 GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26),
201 GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24),
202 GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20),
203 GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19),
204 GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18),
205 GATE_BUS(HCLK_HSMMC0, "hclk_hsmmc0", "hclk", HCLK_GATE, 17),
206 GATE_BUS(HCLK_MDP, "hclk_mdp", "hclk", HCLK_GATE, 16),
207 GATE_BUS(HCLK_DHOST, "hclk_dhost", "hclk", HCLK_GATE, 15),
208 GATE_BUS(HCLK_IHOST, "hclk_ihost", "hclk", HCLK_GATE, 14),
209 GATE_BUS(HCLK_DMA1, "hclk_dma1", "hclk", HCLK_GATE, 13),
210 GATE_BUS(HCLK_DMA0, "hclk_dma0", "hclk", HCLK_GATE, 12),
211 GATE_BUS(HCLK_JPEG, "hclk_jpeg", "hclk", HCLK_GATE, 11),
212 GATE_BUS(HCLK_CAMIF, "hclk_camif", "hclk", HCLK_GATE, 10),
213 GATE_BUS(HCLK_SCALER, "hclk_scaler", "hclk", HCLK_GATE, 9),
214 GATE_BUS(HCLK_2D, "hclk_2d", "hclk", HCLK_GATE, 8),
215 GATE_BUS(HCLK_TV, "hclk_tv", "hclk", HCLK_GATE, 7),
216 GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5),
217 GATE_BUS(HCLK_ROT, "hclk_rot", "hclk", HCLK_GATE, 4),
218 GATE_BUS(HCLK_LCD, "hclk_lcd", "hclk", HCLK_GATE, 3),
219 GATE_BUS(HCLK_TZIC, "hclk_tzic", "hclk", HCLK_GATE, 2),
220 GATE_ON(HCLK_INTC, "hclk_intc", "hclk", HCLK_GATE, 1),
277 GATE_ON(HCLK_DDR0, "hclk_ddr0", "hclk", HCLK_GATE, 23),
283 GATE_BUS(HCLK_3DSE, "hclk_3dse", "hclk", HCLK_GATE, 31),
284 GATE_ON(HCLK_IROM, "hclk_irom", "hclk", HCLK_GATE, 25),
285 GATE_ON(HCLK_MEM1, "hclk_mem1", "hclk", HCLK_GATE, 22),
286 GATE_ON(HCLK_MEM0, "hclk_mem0", "hclk", HCLK_GATE, 21),
287 GATE_BUS(HCLK_MFC, "hclk_mfc", "hclk", HCLK_GATE, 0),