Lines Matching +full:pll +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file contains the utility functions to register the pll clocks.
15 #include <linux/clk-provider.h>
18 #include "clk-pll.h"
27 /* PLL enable control bit offset in @con_reg register */
29 /* PLL lock status bit offset in @con_reg register */
39 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
44 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
55 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
56 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_round_rate()
60 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_round_rate()
66 return rate_table[i - 1].rate; in samsung_pll_round_rate()
74 return 0; in samsung_pll_disable_early_timeout()
78 /* Wait until the PLL is locked */
79 static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, in samsung_pll_lock_wait() argument
98 while (i-- > 0) { in samsung_pll_lock_wait()
99 if (readl_relaxed(pll->con_reg) & reg_mask) in samsung_pll_lock_wait()
100 return 0; in samsung_pll_lock_wait()
104 ret = -ETIMEDOUT; in samsung_pll_lock_wait()
106 ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val, in samsung_pll_lock_wait()
107 val & reg_mask, 0, PLL_TIMEOUT_US); in samsung_pll_lock_wait()
110 if (ret < 0) in samsung_pll_lock_wait()
111 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); in samsung_pll_lock_wait()
118 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_enable() local
121 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_enable()
122 tmp |= BIT(pll->enable_offs); in samsung_pll3xxx_enable()
123 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_enable()
125 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll3xxx_enable()
130 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_disable() local
133 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_disable()
134 tmp &= ~BIT(pll->enable_offs); in samsung_pll3xxx_disable()
135 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_disable()
142 #define PLL2126_MDIV_MASK (0xff)
143 #define PLL2126_PDIV_MASK (0x3f)
144 #define PLL2126_SDIV_MASK (0x3)
147 #define PLL2126_SDIV_SHIFT (0)
152 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2126_recalc_rate() local
156 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2126_recalc_rate()
175 #define PLL3000_MDIV_MASK (0xff)
176 #define PLL3000_PDIV_MASK (0x3)
177 #define PLL3000_SDIV_MASK (0x3)
180 #define PLL3000_SDIV_SHIFT (0)
185 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3000_recalc_rate() local
189 pll_con = readl_relaxed(pll->con_reg); in samsung_pll3000_recalc_rate()
211 #define PLL35XX_MDIV_MASK (0x3FF)
212 #define PLL35XX_PDIV_MASK (0x3F)
213 #define PLL35XX_SDIV_MASK (0x7)
216 #define PLL35XX_SDIV_SHIFT (0)
223 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_recalc_rate() local
227 pll_con = readl_relaxed(pll->con_reg); in samsung_pll35xx_recalc_rate()
246 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
252 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_set_rate() local
257 rate = samsung_get_pll_settings(pll, drate); in samsung_pll35xx_set_rate()
259 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll35xx_set_rate()
261 return -EINVAL; in samsung_pll35xx_set_rate()
264 tmp = readl_relaxed(pll->con_reg); in samsung_pll35xx_set_rate()
269 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; in samsung_pll35xx_set_rate()
270 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
272 return 0; in samsung_pll35xx_set_rate()
275 /* Set PLL lock time. */ in samsung_pll35xx_set_rate()
276 if (pll->type == pll_142xx) in samsung_pll35xx_set_rate()
277 writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR, in samsung_pll35xx_set_rate()
278 pll->lock_reg); in samsung_pll35xx_set_rate()
280 writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, in samsung_pll35xx_set_rate()
281 pll->lock_reg); in samsung_pll35xx_set_rate()
283 /* Change PLL PMS values */ in samsung_pll35xx_set_rate()
287 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | in samsung_pll35xx_set_rate()
288 (rate->pdiv << PLL35XX_PDIV_SHIFT) | in samsung_pll35xx_set_rate()
289 (rate->sdiv << PLL35XX_SDIV_SHIFT); in samsung_pll35xx_set_rate()
290 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
292 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll35xx_set_rate()
293 if (tmp & BIT(pll->enable_offs)) in samsung_pll35xx_set_rate()
294 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll35xx_set_rate()
296 return 0; in samsung_pll35xx_set_rate()
317 #define PLL36XX_KDIV_MASK (0xFFFF)
318 #define PLL36XX_MDIV_MASK (0x1FF)
319 #define PLL36XX_PDIV_MASK (0x3F)
320 #define PLL36XX_SDIV_MASK (0x7)
323 #define PLL36XX_SDIV_SHIFT (0)
324 #define PLL36XX_KDIV_SHIFT (0)
331 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_recalc_rate() local
336 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_recalc_rate()
337 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_recalc_rate()
359 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || in samsung_pll36xx_mpk_change()
360 rate->kdiv != old_kdiv); in samsung_pll36xx_mpk_change()
366 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_set_rate() local
370 rate = samsung_get_pll_settings(pll, drate); in samsung_pll36xx_set_rate()
372 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll36xx_set_rate()
374 return -EINVAL; in samsung_pll36xx_set_rate()
377 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_set_rate()
378 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_set_rate()
383 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); in samsung_pll36xx_set_rate()
384 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
386 return 0; in samsung_pll36xx_set_rate()
389 /* Set PLL lock time. */ in samsung_pll36xx_set_rate()
390 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll36xx_set_rate()
392 /* Change PLL PMS values */ in samsung_pll36xx_set_rate()
396 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | in samsung_pll36xx_set_rate()
397 (rate->pdiv << PLL36XX_PDIV_SHIFT) | in samsung_pll36xx_set_rate()
398 (rate->sdiv << PLL36XX_SDIV_SHIFT); in samsung_pll36xx_set_rate()
399 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
402 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; in samsung_pll36xx_set_rate()
403 writel_relaxed(pll_con1, pll->con_reg + 4); in samsung_pll36xx_set_rate()
405 if (pll_con0 & BIT(pll->enable_offs)) in samsung_pll36xx_set_rate()
406 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll36xx_set_rate()
408 return 0; in samsung_pll36xx_set_rate()
429 #define PLL0822X_MDIV_MASK (0x3FF)
430 #define PLL0822X_PDIV_MASK (0x3F)
431 #define PLL0822X_SDIV_MASK (0x7)
434 #define PLL0822X_SDIV_SHIFT (0)
441 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0822x_recalc_rate() local
445 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0822x_recalc_rate()
460 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0822x_set_rate() local
464 rate = samsung_get_pll_settings(pll, drate); in samsung_pll0822x_set_rate()
466 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll0822x_set_rate()
468 return -EINVAL; in samsung_pll0822x_set_rate()
471 /* Change PLL PMS values */ in samsung_pll0822x_set_rate()
472 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0822x_set_rate()
476 pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) | in samsung_pll0822x_set_rate()
477 (rate->pdiv << PLL0822X_PDIV_SHIFT) | in samsung_pll0822x_set_rate()
478 (rate->sdiv << PLL0822X_SDIV_SHIFT); in samsung_pll0822x_set_rate()
480 /* Set PLL lock time */ in samsung_pll0822x_set_rate()
481 writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR, in samsung_pll0822x_set_rate()
482 pll->lock_reg); in samsung_pll0822x_set_rate()
485 writel_relaxed(pll_con3, pll->con_reg); in samsung_pll0822x_set_rate()
487 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll0822x_set_rate()
488 if (pll_con3 & BIT(pll->enable_offs)) in samsung_pll0822x_set_rate()
489 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll0822x_set_rate()
491 return 0; in samsung_pll0822x_set_rate()
512 #define PLL0831X_KDIV_MASK (0xFFFF)
513 #define PLL0831X_MDIV_MASK (0x1FF)
514 #define PLL0831X_PDIV_MASK (0x3F)
515 #define PLL0831X_SDIV_MASK (0x7)
518 #define PLL0831X_SDIV_SHIFT (0)
519 #define PLL0831X_KDIV_SHIFT (0)
526 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0831x_recalc_rate() local
531 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0831x_recalc_rate()
532 pll_con5 = readl_relaxed(pll->con_reg + 8); in samsung_pll0831x_recalc_rate()
549 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0831x_set_rate() local
553 rate = samsung_get_pll_settings(pll, drate); in samsung_pll0831x_set_rate()
555 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll0831x_set_rate()
557 return -EINVAL; in samsung_pll0831x_set_rate()
560 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0831x_set_rate()
561 pll_con5 = readl_relaxed(pll->con_reg + 8); in samsung_pll0831x_set_rate()
563 /* Change PLL PMSK values */ in samsung_pll0831x_set_rate()
567 pll_con3 |= (rate->mdiv << PLL0831X_MDIV_SHIFT) | in samsung_pll0831x_set_rate()
568 (rate->pdiv << PLL0831X_PDIV_SHIFT) | in samsung_pll0831x_set_rate()
569 (rate->sdiv << PLL0831X_SDIV_SHIFT); in samsung_pll0831x_set_rate()
572 * kdiv is 16-bit 2's complement (s16), but stored as unsigned int. in samsung_pll0831x_set_rate()
573 * Cast it to u16 to avoid leading 0xffff's in case of negative value. in samsung_pll0831x_set_rate()
575 pll_con5 |= ((u16)rate->kdiv << PLL0831X_KDIV_SHIFT); in samsung_pll0831x_set_rate()
577 /* Set PLL lock time */ in samsung_pll0831x_set_rate()
578 writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg); in samsung_pll0831x_set_rate()
581 writel_relaxed(pll_con3, pll->con_reg); in samsung_pll0831x_set_rate()
582 writel_relaxed(pll_con5, pll->con_reg + 8); in samsung_pll0831x_set_rate()
584 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll0831x_set_rate()
585 if (pll_con3 & BIT(pll->enable_offs)) in samsung_pll0831x_set_rate()
586 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll0831x_set_rate()
588 return 0; in samsung_pll0831x_set_rate()
609 #define PLL45XX_MDIV_MASK (0x3FF)
610 #define PLL45XX_PDIV_MASK (0x3F)
611 #define PLL45XX_SDIV_MASK (0x7)
612 #define PLL45XX_AFC_MASK (0x1F)
615 #define PLL45XX_SDIV_SHIFT (0)
616 #define PLL45XX_AFC_SHIFT (0)
624 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_recalc_rate() local
628 pll_con = readl_relaxed(pll->con_reg); in samsung_pll45xx_recalc_rate()
633 if (pll->type == pll_4508) in samsung_pll45xx_recalc_rate()
634 sdiv = sdiv - 1; in samsung_pll45xx_recalc_rate()
651 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll45xx_mp_change()
652 || old_afc != rate->afc); in samsung_pll45xx_mp_change()
658 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_set_rate() local
663 rate = samsung_get_pll_settings(pll, drate); in samsung_pll45xx_set_rate()
665 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll45xx_set_rate()
667 return -EINVAL; in samsung_pll45xx_set_rate()
670 con0 = readl_relaxed(pll->con_reg); in samsung_pll45xx_set_rate()
671 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
676 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; in samsung_pll45xx_set_rate()
677 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
679 return 0; in samsung_pll45xx_set_rate()
682 /* Set PLL PMS values. */ in samsung_pll45xx_set_rate()
686 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
687 (rate->pdiv << PLL45XX_PDIV_SHIFT) | in samsung_pll45xx_set_rate()
688 (rate->sdiv << PLL45XX_SDIV_SHIFT); in samsung_pll45xx_set_rate()
690 /* Set PLL AFC value. */ in samsung_pll45xx_set_rate()
691 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
693 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
695 /* Set PLL lock time. */ in samsung_pll45xx_set_rate()
696 switch (pll->type) { in samsung_pll45xx_set_rate()
698 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
701 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
708 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
709 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
711 /* Wait for PLL lock */ in samsung_pll45xx_set_rate()
712 return samsung_pll_lock_wait(pll, PLL45XX_LOCKED); in samsung_pll45xx_set_rate()
731 #define PLL46XX_MDIV_MASK (0x1FF)
732 #define PLL1460X_MDIV_MASK (0x3FF)
734 #define PLL46XX_PDIV_MASK (0x3F)
735 #define PLL46XX_SDIV_MASK (0x7)
739 #define PLL46XX_SDIV_SHIFT (0)
741 #define PLL46XX_KDIV_MASK (0xFFFF)
742 #define PLL4650C_KDIV_MASK (0xFFF)
743 #define PLL46XX_KDIV_SHIFT (0)
744 #define PLL46XX_MFR_MASK (0x3F)
745 #define PLL46XX_MRR_MASK (0x1F)
746 #define PLL46XX_KDIV_SHIFT (0)
757 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_recalc_rate() local
761 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_recalc_rate()
762 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll46xx_recalc_rate()
763 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? in samsung_pll46xx_recalc_rate()
767 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : in samsung_pll46xx_recalc_rate()
770 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; in samsung_pll46xx_recalc_rate()
788 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll46xx_mpk_change()
789 || old_kdiv != rate->kdiv); in samsung_pll46xx_mpk_change()
795 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_set_rate() local
800 rate = samsung_get_pll_settings(pll, drate); in samsung_pll46xx_set_rate()
802 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll46xx_set_rate()
804 return -EINVAL; in samsung_pll46xx_set_rate()
807 con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_set_rate()
808 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
813 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; in samsung_pll46xx_set_rate()
814 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
816 return 0; in samsung_pll46xx_set_rate()
819 /* Set PLL lock time. */ in samsung_pll46xx_set_rate()
820 lock = rate->pdiv * PLL46XX_LOCK_FACTOR; in samsung_pll46xx_set_rate()
821 if (lock > 0xffff) in samsung_pll46xx_set_rate()
822 /* Maximum lock time bitfield is 16-bit. */ in samsung_pll46xx_set_rate()
823 lock = 0xffff; in samsung_pll46xx_set_rate()
825 /* Set PLL PMS and VSEL values. */ in samsung_pll46xx_set_rate()
826 if (pll->type == pll_1460x) { in samsung_pll46xx_set_rate()
835 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; in samsung_pll46xx_set_rate()
838 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | in samsung_pll46xx_set_rate()
839 (rate->pdiv << PLL46XX_PDIV_SHIFT) | in samsung_pll46xx_set_rate()
840 (rate->sdiv << PLL46XX_SDIV_SHIFT); in samsung_pll46xx_set_rate()
842 /* Set PLL K, MFR and MRR values. */ in samsung_pll46xx_set_rate()
843 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
847 con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) | in samsung_pll46xx_set_rate()
848 (rate->mfr << PLL46XX_MFR_SHIFT) | in samsung_pll46xx_set_rate()
849 (rate->mrr << PLL46XX_MRR_SHIFT); in samsung_pll46xx_set_rate()
851 /* Write configuration to PLL */ in samsung_pll46xx_set_rate()
852 writel_relaxed(lock, pll->lock_reg); in samsung_pll46xx_set_rate()
853 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
854 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
856 /* Wait for PLL lock */ in samsung_pll46xx_set_rate()
857 return samsung_pll_lock_wait(pll, PLL46XX_LOCKED); in samsung_pll46xx_set_rate()
874 #define PLL6552_MDIV_MASK 0x3ff
875 #define PLL6552_PDIV_MASK 0x3f
876 #define PLL6552_SDIV_MASK 0x7
881 #define PLL6552_SDIV_SHIFT 0
886 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6552_recalc_rate() local
890 pll_con = readl_relaxed(pll->con_reg); in samsung_pll6552_recalc_rate()
891 if (pll->type == pll_6552_s3c2416) { in samsung_pll6552_recalc_rate()
914 #define PLL6553_MDIV_MASK 0xff
915 #define PLL6553_PDIV_MASK 0x3f
916 #define PLL6553_SDIV_MASK 0x7
917 #define PLL6553_KDIV_MASK 0xffff
920 #define PLL6553_SDIV_SHIFT 0
921 #define PLL6553_KDIV_SHIFT 0
926 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6553_recalc_rate() local
930 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll6553_recalc_rate()
931 pll_con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll6553_recalc_rate()
952 #define PLL2550X_R_MASK (0x1)
953 #define PLL2550X_P_MASK (0x3F)
954 #define PLL2550X_M_MASK (0x3FF)
955 #define PLL2550X_S_MASK (0x7)
959 #define PLL2550X_S_SHIFT (0)
964 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550x_recalc_rate() local
968 pll_stat = readl_relaxed(pll->con_reg); in samsung_pll2550x_recalc_rate()
971 return 0; in samsung_pll2550x_recalc_rate()
993 #define PLL2550XX_M_MASK 0x3FF
994 #define PLL2550XX_P_MASK 0x3F
995 #define PLL2550XX_S_MASK 0x7
996 #define PLL2550XX_LOCK_STAT_MASK 0x1
999 #define PLL2550XX_S_SHIFT 0
1005 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_recalc_rate() local
1009 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2550xx_recalc_rate()
1033 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_set_rate() local
1038 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2550xx_set_rate()
1040 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2550xx_set_rate()
1042 return -EINVAL; in samsung_pll2550xx_set_rate()
1045 tmp = readl_relaxed(pll->con_reg); in samsung_pll2550xx_set_rate()
1047 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { in samsung_pll2550xx_set_rate()
1050 tmp |= rate->sdiv << PLL2550XX_S_SHIFT; in samsung_pll2550xx_set_rate()
1051 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1053 return 0; in samsung_pll2550xx_set_rate()
1056 /* Set PLL lock time. */ in samsung_pll2550xx_set_rate()
1057 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll2550xx_set_rate()
1059 /* Change PLL PMS values */ in samsung_pll2550xx_set_rate()
1063 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | in samsung_pll2550xx_set_rate()
1064 (rate->pdiv << PLL2550XX_P_SHIFT) | in samsung_pll2550xx_set_rate()
1065 (rate->sdiv << PLL2550XX_S_SHIFT); in samsung_pll2550xx_set_rate()
1066 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1068 /* Wait for PLL lock */ in samsung_pll2550xx_set_rate()
1069 return samsung_pll_lock_wait(pll, in samsung_pll2550xx_set_rate()
1090 #define PLL2650X_M_MASK 0x1ff
1091 #define PLL2650X_P_MASK 0x3f
1092 #define PLL2650X_S_MASK 0x7
1093 #define PLL2650X_K_MASK 0xffff
1094 #define PLL2650X_LOCK_STAT_MASK 0x1
1097 #define PLL2650X_S_SHIFT 0
1098 #define PLL2650X_K_SHIFT 0
1105 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_recalc_rate() local
1110 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_recalc_rate()
1115 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_recalc_rate()
1128 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_set_rate() local
1133 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2650x_set_rate()
1135 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2650x_set_rate()
1137 return -EINVAL; in samsung_pll2650x_set_rate()
1140 con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_set_rate()
1141 con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_set_rate()
1143 /* Set PLL lock time. */ in samsung_pll2650x_set_rate()
1144 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg); in samsung_pll2650x_set_rate()
1146 /* Change PLL PMS values */ in samsung_pll2650x_set_rate()
1150 con0 |= (rate->mdiv << PLL2650X_M_SHIFT) | in samsung_pll2650x_set_rate()
1151 (rate->pdiv << PLL2650X_P_SHIFT) | in samsung_pll2650x_set_rate()
1152 (rate->sdiv << PLL2650X_S_SHIFT); in samsung_pll2650x_set_rate()
1154 writel_relaxed(con0, pll->con_reg); in samsung_pll2650x_set_rate()
1157 con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT); in samsung_pll2650x_set_rate()
1158 writel_relaxed(con1, pll->con_reg + 4); in samsung_pll2650x_set_rate()
1160 /* Wait for PLL lock */ in samsung_pll2650x_set_rate()
1161 return samsung_pll_lock_wait(pll, in samsung_pll2650x_set_rate()
1184 #define PLL2650XX_SDIV_SHIFT 0
1185 #define PLL2650XX_KDIV_SHIFT 0
1186 #define PLL2650XX_MDIV_MASK 0x1ff
1187 #define PLL2650XX_PDIV_MASK 0x3f
1188 #define PLL2650XX_SDIV_MASK 0x7
1189 #define PLL2650XX_KDIV_MASK 0xffff
1197 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_recalc_rate() local
1202 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_recalc_rate()
1203 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_recalc_rate()
1219 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_set_rate() local
1223 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2650xx_set_rate()
1225 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2650xx_set_rate()
1227 return -EINVAL; in samsung_pll2650xx_set_rate()
1230 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_set_rate()
1231 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1233 /* Change PLL PMS values */ in samsung_pll2650xx_set_rate()
1237 pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; in samsung_pll2650xx_set_rate()
1238 pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; in samsung_pll2650xx_set_rate()
1239 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; in samsung_pll2650xx_set_rate()
1244 pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) in samsung_pll2650xx_set_rate()
1247 /* Set PLL lock time. */ in samsung_pll2650xx_set_rate()
1248 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); in samsung_pll2650xx_set_rate()
1250 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll2650xx_set_rate()
1251 writel_relaxed(pll_con2, pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1253 return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT); in samsung_pll2650xx_set_rate()
1269 struct samsung_clk_pll *pll; in _samsung_clk_register_pll() local
1273 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in _samsung_clk_register_pll()
1274 if (!pll) { in _samsung_clk_register_pll()
1275 pr_err("%s: could not allocate pll clk %s\n", in _samsung_clk_register_pll()
1276 __func__, pll_clk->name); in _samsung_clk_register_pll()
1280 init.name = pll_clk->name; in _samsung_clk_register_pll()
1281 init.flags = pll_clk->flags; in _samsung_clk_register_pll()
1282 init.parent_names = &pll_clk->parent_name; in _samsung_clk_register_pll()
1285 if (pll_clk->rate_table) { in _samsung_clk_register_pll()
1287 for (len = 0; pll_clk->rate_table[len].rate != 0; ) in _samsung_clk_register_pll()
1290 pll->rate_count = len; in _samsung_clk_register_pll()
1291 pll->rate_table = kmemdup(pll_clk->rate_table, in _samsung_clk_register_pll()
1292 pll->rate_count * in _samsung_clk_register_pll()
1295 WARN(!pll->rate_table, in _samsung_clk_register_pll()
1297 __func__, pll_clk->name); in _samsung_clk_register_pll()
1300 switch (pll_clk->type) { in _samsung_clk_register_pll()
1314 pll->enable_offs = PLL35XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1315 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1316 if (!pll->rate_table) in _samsung_clk_register_pll()
1324 pll->enable_offs = PLL0822X_ENABLE_SHIFT; in _samsung_clk_register_pll()
1325 pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1326 if (!pll->rate_table) in _samsung_clk_register_pll()
1336 if (!pll->rate_table) in _samsung_clk_register_pll()
1344 pll->enable_offs = PLL36XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1345 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1346 if (!pll->rate_table) in _samsung_clk_register_pll()
1352 pll->enable_offs = PLL0831X_ENABLE_SHIFT; in _samsung_clk_register_pll()
1353 pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1354 if (!pll->rate_table) in _samsung_clk_register_pll()
1370 if (!pll->rate_table) in _samsung_clk_register_pll()
1379 if (!pll->rate_table) in _samsung_clk_register_pll()
1385 if (!pll->rate_table) in _samsung_clk_register_pll()
1391 if (!pll->rate_table) in _samsung_clk_register_pll()
1397 pr_warn("%s: Unknown pll type for pll clk %s\n", in _samsung_clk_register_pll()
1398 __func__, pll_clk->name); in _samsung_clk_register_pll()
1401 pll->hw.init = &init; in _samsung_clk_register_pll()
1402 pll->type = pll_clk->type; in _samsung_clk_register_pll()
1403 pll->lock_reg = ctx->reg_base + pll_clk->lock_offset; in _samsung_clk_register_pll()
1404 pll->con_reg = ctx->reg_base + pll_clk->con_offset; in _samsung_clk_register_pll()
1406 ret = clk_hw_register(ctx->dev, &pll->hw); in _samsung_clk_register_pll()
1408 pr_err("%s: failed to register pll clock %s : %d\n", in _samsung_clk_register_pll()
1409 __func__, pll_clk->name, ret); in _samsung_clk_register_pll()
1410 kfree(pll->rate_table); in _samsung_clk_register_pll()
1411 kfree(pll); in _samsung_clk_register_pll()
1415 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); in _samsung_clk_register_pll()
1424 for (cnt = 0; cnt < nr_pll; cnt++) in samsung_clk_register_pll()