Lines Matching refs:ENABLE_SCLK_PERIC
1577 #define ENABLE_SCLK_PERIC 0x0A00 macro
1587 ENABLE_SCLK_PERIC,
1597 { ENABLE_SCLK_PERIC, 0x7 },
1706 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1708 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1709 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1711 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1713 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1715 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1717 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1719 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1721 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
1723 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1725 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1728 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1730 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1732 ENABLE_SCLK_PERIC, 6,
1734 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1736 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1738 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1741 ENABLE_SCLK_PERIC, 2,
1744 ENABLE_SCLK_PERIC, 1,
1747 ENABLE_SCLK_PERIC, 0,