Lines Matching refs:E5420_EGL_DIV0

1489 #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud)			\  macro
1494 	{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1495 	{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1496 	{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1497 	{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1498 	{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1499 	{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1500 	{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1501 	{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1502 	{ 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
1503 	{  900000, E5420_EGL_DIV0(3, 6, 6, 2), },
1504 	{  800000, E5420_EGL_DIV0(3, 5, 5, 2), },
1505 	{  700000, E5420_EGL_DIV0(3, 5, 5, 2), },
1506 	{  600000, E5420_EGL_DIV0(3, 4, 4, 2), },
1507 	{  500000, E5420_EGL_DIV0(3, 3, 3, 2), },
1508 	{  400000, E5420_EGL_DIV0(3, 3, 3, 2), },
1509 	{  300000, E5420_EGL_DIV0(3, 3, 3, 2), },
1510 	{  200000, E5420_EGL_DIV0(3, 3, 3, 2), },
1515 	{ 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
1516 	{ 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
1517 	{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1518 	{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1519 	{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1520 	{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1521 	{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1522 	{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1523 	{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1524 	{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1525 	{ 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
1526 	{  900000, E5420_EGL_DIV0(3, 7, 6, 2), },
1527 	{  800000, E5420_EGL_DIV0(3, 7, 5, 2), },
1528 	{  700000, E5420_EGL_DIV0(3, 7, 5, 2), },
1529 	{  600000, E5420_EGL_DIV0(3, 7, 4, 2), },
1530 	{  500000, E5420_EGL_DIV0(3, 7, 3, 2), },
1531 	{  400000, E5420_EGL_DIV0(3, 7, 3, 2), },
1532 	{  300000, E5420_EGL_DIV0(3, 7, 3, 2), },
1533 	{  200000, E5420_EGL_DIV0(3, 7, 3, 2), },