clk/samsung/clk-exynos4.c

283 PNAME(mout_apll_p)	= { "fin_pll", "fout_apll", };
284 PNAME(mout_mpll_p)	= { "fin_pll", "fout_mpll", };
285 PNAME(mout_epll_p)	= { "fin_pll", "fout_epll", };
286 PNAME(mout_vpllsrc_p)	= { "fin_pll", "sclk_hdmi24m", };
287 PNAME(mout_vpll_p)	= { "fin_pll", "fout_vpll", };
339 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
357 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
358 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
359 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
1014  * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
1016  * mapped space. So to determine the parent of fin_pll clock, the chipid
1052 			"fin_pll clock frequency is 24MHz\n", __func__,  in exynos4_clk_register_finpll()
1059 	fclk.name = "fin_pll";  in exynos4_clk_register_finpll()
1151 	[apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1153 	[mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1155 	[epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1162 	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1164 	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1166 	[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1168 	[vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",