clk/samsung/clk-exynos4.c

1 // SPDX-License-Identifier: GPL-2.0-only
7  * Common Clock Framework support for all Exynos4 SoCs.
10 #include <dt-bindings/clock/exynos4.h>
13 #include <linux/clk-provider.h>
19 #include "clk-cpu.h"
21 /* Exynos4 clock controller register offsets */
138 /* NOTE: Must be equal to the last clock ID increased by one */
282 /* list of all parent clock list */
299 /* Exynos 4210-specific parent groups */
303 PNAME(group1_p4210)	= { "xxti", "xusbxti", "sclk_hdmi24m",
307 				"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
310 				"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
313 				"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
317 PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
338 /* Exynos 4x12-specific parent groups */
344 PNAME(group1_p4x12)	= { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
348 				"sclk_usbphy0", "xxti", "xusbxti",
351 				"sclk_usbphy0", "xxti", "xusbxti",
354 				"sclk_usbphy0", "xxti", "xusbxti",
360 PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
389 	FRATE(CLK_XXTI, "xxti", NULL, 0, 0),
878 	GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
1014  * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
1015  * resides in chipid register space, outside of the clock controller memory
1016  * mapped space. So to determine the parent of fin_pll clock, the chipid
1018  * determine the parent clock.
1026 	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");  in exynos4_get_xom()
1048 	parent_name = xom & 1 ? "xusbxti" : "xxti";  in exynos4_clk_register_finpll()
1051 		pr_err("%s: failed to lookup parent clock %s, assuming "  in exynos4_clk_register_finpll()
1052 			"fin_pll clock frequency is 24MHz\n", __func__,  in exynos4_clk_register_finpll()
1068 	{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
1069 	{ .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
1128 	PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690),
1177 	 * Enable arm clock down (in idle) and set arm divider  in exynos4x12_core_down_clock()
1191 	 * Disable the clock up feature in case it was enabled by bootloader.  in exynos4x12_core_down_clock()
1282 	hws = ctx->clk_data.hws;  in exynos4_clk_init()
1395 CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
1401 CLK_OF_DECLARE(exynos4212_clk, "samsung,exynos4212-clock", exynos4212_clk_init);
1407 CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);