clk/rockchip/clk-rk3128.c

130 PNAME(mux_pll_p)		= { "clk_24m", "xin24m" };
132 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_div2_ddr" };
133 PNAME(mux_armclk_p)		= { "apll_core", "gpll_div2_core" };
134 PNAME(mux_usb480m_p)		= { "usb480m_phy", "xin24m" };
135 PNAME(mux_aclk_cpu_src_p)	= { "cpll", "gpll", "gpll_div2", "gpll_div3" };
137 PNAME(mux_pll_src_5plls_p)	= { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480m" };
138 PNAME(mux_pll_src_4plls_p)	= { "cpll", "gpll", "gpll_div2", "usb480m" };
139 PNAME(mux_pll_src_3plls_p)	= { "cpll", "gpll", "gpll_div2" };
141 PNAME(mux_clk_peri_src_p)	= { "gpll", "cpll", "gpll_div2", "gpll_div3" };
142 PNAME(mux_mmc_src_p)		= { "cpll", "gpll", "gpll_div2", "xin24m" };
143 PNAME(mux_clk_cif_out_src_p)		= { "clk_cif_src", "xin24m" };
144 PNAME(mux_sclk_vop_src_p)	= { "cpll", "gpll", "gpll_div2", "gpll_div3" };
146 PNAME(mux_i2s0_p)		= { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
147 PNAME(mux_i2s1_pre_p)		= { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" };
148 PNAME(mux_i2s_out_p)		= { "i2s1_pre", "xin12m" };
149 PNAME(mux_sclk_spdif_p)		= { "sclk_spdif_src", "spdif_frac", "xin12m" };
151 PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
152 PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
153 PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };
155 PNAME(mux_sclk_gmac_p)	= { "sclk_gmac_src", "gmac_clkin" };
156 PNAME(mux_sclk_sfc_src_p)	= { "cpll", "gpll", "gpll_div2", "xin24m" };