584 #define RK3399_PLLCON(i)			(i * 0x4)  macro
609 	ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),  in rockchip_rk3399_pll_wait_lock()
624 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));  in rockchip_rk3399_pll_get_params()
628 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));  in rockchip_rk3399_pll_get_params()
636 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3399_pll_get_params()
640 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_get_params()
698 		       pll->reg_base + RK3399_PLLCON(0));  in rockchip_rk3399_pll_set_params()
706 		       pll->reg_base + RK3399_PLLCON(1));  in rockchip_rk3399_pll_set_params()
709 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3399_pll_set_params()
712 	writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3399_pll_set_params()
716 		       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_set_params()
757 	       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_enable()
769 	       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_disable()
775 	u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_is_enabled()
947 	       pll->reg_base + RK3399_PLLCON(1));  in rockchip_rk3588_pll_set_params()
951 		       pll->reg_base + RK3399_PLLCON(0));  in rockchip_rk3588_pll_set_params()
955 		       pll->reg_base + RK3399_PLLCON(1));  in rockchip_rk3588_pll_set_params()
958 		       pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3588_pll_set_params()