1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
41  * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
54 	/* Constant signal, no measurable phase shift */  in rockchip_mmc_get_phase()
58 	raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);  in rockchip_mmc_get_phase()
85 	 * The below calculation is based on the output clock from  in rockchip_mmc_set_phase()
86 	 * MMC host to the card, which expects the phase clock inherits  in rockchip_mmc_set_phase()
87 	 * the clock rate from its parent, namely the output clock  in rockchip_mmc_set_phase()
98 		return -EINVAL;  in rockchip_mmc_set_phase()
106 	 * actually go non-monotonic.  We don't go _too_ monotonic  in rockchip_mmc_set_phase()
125 	 * don't overflow 32-bit / 64-bit numbers.  in rockchip_mmc_set_phase()
138 	writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),  in rockchip_mmc_set_phase()
139 	       mmc_clock->reg);  in rockchip_mmc_set_phase()
141 	pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",  in rockchip_mmc_set_phase()
143 		mmc_clock->reg, raw_value>>(mmc_clock->shift),  in rockchip_mmc_set_phase()
166 	 * the intput data, which expects the fixed phase after the tuning  in rockchip_mmc_clk_rate_notify()
167 	 * process. However if the clock rate is changed, the phase is stale  in rockchip_mmc_clk_rate_notify()
168 	 * and may break the data sampling. So here we try to restore the phase  in rockchip_mmc_clk_rate_notify()
171 	 * clock provider be reparented from orphan to its real parent in the  in rockchip_mmc_clk_rate_notify()
173 	 * since we only set the default sample phase and drive phase later on.  in rockchip_mmc_clk_rate_notify()
175 	 * set the max-frequency to match the boards' ability but we can't go  in rockchip_mmc_clk_rate_notify()
178 	if (ndata->old_rate <= ndata->new_rate)  in rockchip_mmc_clk_rate_notify()
182 		mmc_clock->cached_phase =  in rockchip_mmc_clk_rate_notify()
183 			rockchip_mmc_get_phase(&mmc_clock->hw);  in rockchip_mmc_clk_rate_notify()
184 	else if (mmc_clock->cached_phase != -EINVAL &&  in rockchip_mmc_clk_rate_notify()
186 		rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase);  in rockchip_mmc_clk_rate_notify()
202 		return ERR_PTR(-ENOMEM);  in rockchip_clk_register_mmc()
210 	mmc_clock->hw.init = &init;  in rockchip_clk_register_mmc()
211 	mmc_clock->reg = reg;  in rockchip_clk_register_mmc()
212 	mmc_clock->shift = shift;  in rockchip_clk_register_mmc()
214 	clk = clk_register(NULL, &mmc_clock->hw);  in rockchip_clk_register_mmc()
220 	mmc_clock->clk_rate_change_nb.notifier_call =  in rockchip_clk_register_mmc()
222 	ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb);  in rockchip_clk_register_mmc()