186 	struct sd_hw_data *hwdata = to_sd_hw_data(hw);  in rzg2l_cpg_sd_clk_mux_set_parent()  local
187 	struct rzg2l_cpg_priv *priv = hwdata->priv;  in rzg2l_cpg_sd_clk_mux_set_parent()
188 	u32 off = GET_REG_OFFSET(hwdata->conf);  in rzg2l_cpg_sd_clk_mux_set_parent()
189 	u32 shift = GET_SHIFT(hwdata->conf);  in rzg2l_cpg_sd_clk_mux_set_parent()
206 	bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;  in rzg2l_cpg_sd_clk_mux_set_parent()
235 	struct sd_hw_data *hwdata = to_sd_hw_data(hw);  in rzg2l_cpg_sd_clk_mux_get_parent()  local
236 	struct rzg2l_cpg_priv *priv = hwdata->priv;  in rzg2l_cpg_sd_clk_mux_get_parent()
237 	u32 val = readl(priv->base + GET_REG_OFFSET(hwdata->conf));  in rzg2l_cpg_sd_clk_mux_get_parent()
239 	val >>= GET_SHIFT(hwdata->conf);  in rzg2l_cpg_sd_clk_mux_get_parent()
240 	val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0);  in rzg2l_cpg_sd_clk_mux_get_parent()
439 	struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);  in rzg2l_cpg_pll5_4_clk_mux_determine_rate()  local
440 	struct rzg2l_cpg_priv *priv = hwdata->priv;  in rzg2l_cpg_pll5_4_clk_mux_determine_rate()
451 	struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);  in rzg2l_cpg_pll5_4_clk_mux_set_parent()  local
452 	struct rzg2l_cpg_priv *priv = hwdata->priv;  in rzg2l_cpg_pll5_4_clk_mux_set_parent()
472 	struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);  in rzg2l_cpg_pll5_4_clk_mux_get_parent()  local
473 	struct rzg2l_cpg_priv *priv = hwdata->priv;  in rzg2l_cpg_pll5_4_clk_mux_get_parent()
475 	return readl(priv->base + GET_REG_OFFSET(hwdata->conf));  in rzg2l_cpg_pll5_4_clk_mux_get_parent()