clk/renesas/rcar-gen4-cpg.c

31 #define CPG_PLLECR		0x0820	/* PLL Enable Control Register */
36 #define CPG_PLL1CR0		0x830	/* PLLn Control Registers */
37 #define CPG_PLL1CR1		0x8b0
38 #define CPG_PLL2CR0		0x834
39 #define CPG_PLL2CR1		0x8b8
40 #define CPG_PLL3CR0		0x83c
41 #define CPG_PLL3CR1		0x8c0
42 #define CPG_PLL4CR0		0x844
43 #define CPG_PLL4CR1		0x8c8
44 #define CPG_PLL6CR0		0x84c
45 #define CPG_PLL6CR1		0x8d8
54 #define CPG_PLLxCR0_SSDEPT	GENMASK(6, 0)	/* SSCG Modulation Depth */
58 #define SSMODE_CENTER		BIT(0)	/* Center (vs. Down) Spread Dithering */
97 	return 0;  in cpg_pll_clk_determine_rate()
120 	cpg_reg_modify(pll_clk->pllcr0_reg, 0, CPG_PLLxCR0_KICK);  in cpg_pll_clk_set_rate()
132 				  val & pll_clk->pllecr_pllst_mask, 0, 1000);  in cpg_pll_clk_set_rate()
168 	writel(0, base + cr1_offset);  in cpg_pll_clk_register()
169 	cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_SSMODE, 0);  in cpg_pll_clk_register()
180 #define CPG_FRQCRB			0x00000804
182 #define CPG_FRQCRC			0x00000808
237 	return 0;  in cpg_z_clk_determine_rate()
260 	cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);  in cpg_z_clk_set_rate()
273 			return 0;  in cpg_z_clk_set_rate()
328 	{ 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
341 	parent = clks[core->parent & 0xffff];	/* some types use high bits */  in rcar_gen4_cpg_clk_register()
391 		mult = (((value >> 24) & 0x7f) + 1) * 2;  in rcar_gen4_cpg_clk_register()
399 		div = ((readl(base + SD0CKCR1) >> 29) & 0x03) + 4;  in rcar_gen4_cpg_clk_register()
416 			div = core->div & 0xffff;  in rcar_gen4_cpg_clk_register()
435 						  __clk_get_name(parent), 0,  in rcar_gen4_cpg_clk_register()
436 						  base + CPG_RPCCKCR, 3, 2, 0,  in rcar_gen4_cpg_clk_register()
453 					 __clk_get_name(parent), 0, mult, div);  in rcar_gen4_cpg_clk_register()
465 	return 0;  in rcar_gen4_cpg_init()