Lines Matching refs:D_DIV
192 #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \ macro
262 D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
267 D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250),
268 D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16),
269 D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32),
270 D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200),
271 D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128),
272 D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128),
273 D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128),
274 D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40),
275 D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64),
276 D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7),
277 D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7),
278 D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16),
279 D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128),
280 D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128),
281 D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40),
282 D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128),
397 D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8),
443 D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
465 D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640),