1 // SPDX-License-Identifier: GPL-2.0
3  * r8a7790 Common Clock Framework support
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27  * struct div6_clock - CPG 6 bit divider clock
28  * @hw: handle between common and hardware-specific interfaces
29  * @reg: IO-remapped register
30  * @div: divisor value (1-64)
31  * @src_mask: Bitmask covering the register bits to select the parent clock
32  * @nb: Notifier block to save/restore clock state for system resume
38 	unsigned int div;  member
48 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_enable()  local
51 	val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))  in cpg_div6_clock_enable()
52 	    | CPG_DIV6_DIV(clock->div - 1);  in cpg_div6_clock_enable()
53 	writel(val, clock->reg);  in cpg_div6_clock_enable()
60 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_disable()  local
63 	val = readl(clock->reg);  in cpg_div6_clock_disable()
66 	 * DIV6 clocks require the divisor field to be non-zero when stopping  in cpg_div6_clock_disable()
67 	 * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be  in cpg_div6_clock_disable()
68 	 * re-enabled later if the divisor field is changed when stopping the  in cpg_div6_clock_disable()
69 	 * clock  in cpg_div6_clock_disable()
73 	writel(val, clock->reg);  in cpg_div6_clock_disable()
78 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_is_enabled()  local
80 	return !(readl(clock->reg) & CPG_DIV6_CKSTP);  in cpg_div6_clock_is_enabled()
86 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_recalc_rate()  local
88 	return parent_rate / clock->div;  in cpg_div6_clock_recalc_rate()
94 	unsigned int div;  in cpg_div6_clock_calc_div()  local
99 	div = DIV_ROUND_CLOSEST(parent_rate, rate);  in cpg_div6_clock_calc_div()
100 	return clamp(div, 1U, 64U);  in cpg_div6_clock_calc_div()
109 	unsigned int i, min_div, max_div, div;  in cpg_div6_clock_determine_rate()  local
121 		min_div = max(DIV_ROUND_UP(prate, req->max_rate), 1UL);  in cpg_div6_clock_determine_rate()
122 		max_div = req->min_rate ? min(prate / req->min_rate, 64UL) : 64;  in cpg_div6_clock_determine_rate()
126 		div = cpg_div6_clock_calc_div(req->rate, prate);  in cpg_div6_clock_determine_rate()
127 		div = clamp(div, min_div, max_div);  in cpg_div6_clock_determine_rate()
128 		calc_rate = prate / div;  in cpg_div6_clock_determine_rate()
129 		diff = calc_rate > req->rate ? calc_rate - req->rate  in cpg_div6_clock_determine_rate()
130 					     : req->rate - calc_rate;  in cpg_div6_clock_determine_rate()
140 		return -EINVAL;  in cpg_div6_clock_determine_rate()
142 	req->best_parent_rate = best_prate;  in cpg_div6_clock_determine_rate()
143 	req->best_parent_hw = best_parent;  in cpg_div6_clock_determine_rate()
144 	req->rate = best_rate;  in cpg_div6_clock_determine_rate()
151 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_set_rate()  local
152 	unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);  in cpg_div6_clock_set_rate()  local
155 	clock->div = div;  in cpg_div6_clock_set_rate()
157 	val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK;  in cpg_div6_clock_set_rate()
158 	/* Only program the new divisor if the clock isn't stopped. */  in cpg_div6_clock_set_rate()
160 		writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);  in cpg_div6_clock_set_rate()
167 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_get_parent()  local
171 	if (clock->src_mask == 0)  in cpg_div6_clock_get_parent()
174 	hw_index = (readl(clock->reg) & clock->src_mask) >>  in cpg_div6_clock_get_parent()
175 		   __ffs(clock->src_mask);  in cpg_div6_clock_get_parent()
177 		if (clock->parents[i] == hw_index)  in cpg_div6_clock_get_parent()
181 	pr_err("%s: %s DIV6 clock set to invalid parent %u\n",  in cpg_div6_clock_get_parent()
188 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_set_parent()  local
192 		return -EINVAL;  in cpg_div6_clock_set_parent()
194 	src = clock->parents[index] << __ffs(clock->src_mask);  in cpg_div6_clock_set_parent()
195 	writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg);  in cpg_div6_clock_set_parent()
213 	struct div6_clock *clock = container_of(nb, struct div6_clock, nb);  in cpg_div6_clock_notifier_call()  local
221 		 * R/SH-Mobile SoCs, while the resume functionality is only  in cpg_div6_clock_notifier_call()
222 		 * needed on R-Car Gen3.  in cpg_div6_clock_notifier_call()
224 		if (__clk_get_enable_count(clock->hw.clk))  in cpg_div6_clock_notifier_call()
225 			cpg_div6_clock_enable(&clock->hw);  in cpg_div6_clock_notifier_call()
227 			cpg_div6_clock_disable(&clock->hw);  in cpg_div6_clock_notifier_call()
235  * cpg_div6_register - Register a DIV6 clock
236  * @name: Name of the DIV6 clock
237  * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
239  * @reg: Mapped register used to control the DIV6 clock
250 	struct div6_clock *clock;  in cpg_div6_register()  local
254 	clock = kzalloc(struct_size(clock, parents, num_parents), GFP_KERNEL);  in cpg_div6_register()
255 	if (!clock)  in cpg_div6_register()
256 		return ERR_PTR(-ENOMEM);  in cpg_div6_register()
258 	clock->reg = reg;  in cpg_div6_register()
261 	 * Read the divisor. Disabling the clock overwrites the divisor, so we  in cpg_div6_register()
264 	clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;  in cpg_div6_register()
268 		/* fixed parent clock */  in cpg_div6_register()
269 		clock->src_mask = 0;  in cpg_div6_register()
272 		/* clock with EXSRC bits 6-7 */  in cpg_div6_register()
273 		clock->src_mask = GENMASK(7, 6);  in cpg_div6_register()
276 		/* VCLK with EXSRC bits 12-14 */  in cpg_div6_register()
277 		clock->src_mask = GENMASK(14, 12);  in cpg_div6_register()
280 		pr_err("%s: invalid number of parents for DIV6 clock %s\n",  in cpg_div6_register()
282 		clk = ERR_PTR(-EINVAL);  in cpg_div6_register()
290 			clock->parents[valid_parents] = i;  in cpg_div6_register()
295 	/* Register the clock. */  in cpg_div6_register()
301 	clock->hw.init = &init;  in cpg_div6_register()
303 	clk = clk_register(NULL, &clock->hw);  in cpg_div6_register()
308 		clock->nb.notifier_call = cpg_div6_clock_notifier_call;  in cpg_div6_register()
309 		raw_notifier_chain_register(notifiers, &clock->nb);  in cpg_div6_register()
315 	kfree(clock);  in cpg_div6_register()
323 	const char *clk_name = np->name;  in cpg_div6_clock_init()
330 		pr_err("%s: no parent found for %pOFn DIV6 clock\n",  in cpg_div6_clock_init()
342 		pr_err("%s: failed to map %pOFn DIV6 clock register\n",  in cpg_div6_clock_init()
348 	of_property_read_string(np, "clock-output-names", &clk_name);  in cpg_div6_clock_init()
355 		pr_err("%s: failed to register %pOFn DIV6 clock (%ld)\n",  in cpg_div6_clock_init()
370 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);