Lines Matching +full:0 +full:x80b0
35 { 249600000, 2020000000, 0 },
40 .l = 0x0044001e,
41 .alpha = 0x0,
42 .config_ctl_val = 0x20485699,
43 .config_ctl_hi_val = 0x00182261,
44 .config_ctl_hi1_val = 0x32aa299c,
45 .user_ctl_val = 0x00000000,
46 .user_ctl_hi_val = 0x00000805,
50 .offset = 0x0,
68 .l = 0x0044002b,
69 .alpha = 0xc000,
70 .config_ctl_val = 0x20485699,
71 .config_ctl_hi_val = 0x00182261,
72 .config_ctl_hi1_val = 0x32aa299c,
73 .user_ctl_val = 0x00000000,
74 .user_ctl_hi_val = 0x00000805,
78 .offset = 0x1000,
95 { P_BI_TCXO, 0 },
105 { P_BI_TCXO, 0 },
115 F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
116 F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
117 F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
118 F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
119 F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
124 .cmd_rcgr = 0x8000,
125 .mnd_width = 0,
139 F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
140 F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
141 F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
142 F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
143 F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
148 .cmd_rcgr = 0x8018,
149 .mnd_width = 0,
163 .reg = 0x80b8,
164 .shift = 0,
178 .reg = 0x806c,
179 .shift = 0,
193 .reg = 0x80dc,
194 .shift = 0,
208 .reg = 0x8094,
209 .shift = 0,
223 .halt_reg = 0x80b0,
225 .hwcg_reg = 0x80b0,
228 .enable_reg = 0x80b0,
229 .enable_mask = BIT(0),
243 .halt_reg = 0x8064,
246 .enable_reg = 0x8064,
247 .enable_mask = BIT(0),
261 .halt_reg = 0x80d4,
263 .hwcg_reg = 0x80d4,
266 .enable_reg = 0x80d4,
267 .enable_mask = BIT(0),
281 .halt_reg = 0x808c,
284 .enable_reg = 0x808c,
285 .enable_mask = BIT(0),
299 .gdscr = 0x804c,
300 .en_rest_wait_val = 0x2,
301 .en_few_wait_val = 0x2,
302 .clk_dis_wait_val = 0x6,
311 .gdscr = 0x809c,
312 .en_rest_wait_val = 0x2,
313 .en_few_wait_val = 0x2,
314 .clk_dis_wait_val = 0x6,
324 .gdscr = 0x8074,
325 .en_rest_wait_val = 0x2,
326 .en_few_wait_val = 0x2,
327 .clk_dis_wait_val = 0x6,
336 .gdscr = 0x80c0,
337 .en_rest_wait_val = 0x2,
338 .en_few_wait_val = 0x2,
339 .clk_dis_wait_val = 0x6,
371 [CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80e0 },
372 [CVP_VIDEO_CC_MVS0_BCR] = { 0x8098 },
373 [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
374 [CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc },
375 [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 },
376 [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
377 [VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 },
384 .max_register = 0x9f4c,
432 regmap_update_bits(regmap, 0x80e4, BIT(0), BIT(0)); in video_cc_sm8450_probe()
433 regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0)); in video_cc_sm8450_probe()
434 regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0)); in video_cc_sm8450_probe()