Lines Matching +full:0 +full:x42c
27 { 249600000, 2000000000, 0 },
31 .l = 0x14,
32 .alpha = 0xD555,
33 .config_ctl_val = 0x20485699,
34 .config_ctl_hi_val = 0x00002267,
35 .config_ctl_hi1_val = 0x00000024,
36 .test_ctl_hi1_val = 0x00000020,
37 .user_ctl_val = 0x00000000,
38 .user_ctl_hi_val = 0x00000805,
39 .user_ctl_hi1_val = 0x000000D0,
43 .offset = 0x42c,
60 { P_BI_TCXO, 0 },
70 F(19200000, P_BI_TCXO, 1, 0, 0),
71 F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
72 F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
73 F(338000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
74 F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
75 F(444000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
76 F(533000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
81 .cmd_rcgr = 0x7f0,
82 .mnd_width = 0,
96 .halt_reg = 0x8f4,
99 .enable_reg = 0x8f4,
100 .enable_mask = BIT(0),
114 .halt_reg = 0x890,
117 .enable_reg = 0x890,
118 .enable_mask = BIT(0),
132 .halt_reg = 0x8d0,
135 .enable_reg = 0x8d0,
136 .enable_mask = BIT(0),
150 .halt_reg = 0x850,
153 .enable_reg = 0x850,
154 .enable_mask = BIT(0),
168 .gdscr = 0x814,
172 .flags = 0,
177 .gdscr = 0x874,
186 .gdscr = 0x8b4,
212 .max_register = 0xb94,
217 [VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
218 [VIDEO_CC_INTERFACE_BCR] = { 0x8f0 },
219 [VIDEO_CC_MVS0_BCR] = { 0x870 },
220 [VIDEO_CC_MVS1_BCR] = { 0x8b0 },
221 [VIDEO_CC_MVSC_BCR] = { 0x810 },
251 regmap_update_bits(regmap, 0x984, 0x1, 0x1); in video_cc_sm8150_probe()