1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
16 #include <linux/reset-controller.h>
52 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
66 	if (sc->flags & POLL_CFG_GDSCR)  in gdsc_check_status()
67 		reg = sc->gdscr + CFG_GDSCR_OFFSET;  in gdsc_check_status()
68 	else if (sc->gds_hw_ctrl)  in gdsc_check_status()
69 		reg = sc->gds_hw_ctrl;  in gdsc_check_status()
71 		reg = sc->gdscr;  in gdsc_check_status()
73 	ret = regmap_read(sc->regmap, reg, &val);  in gdsc_check_status()
77 	if (sc->flags & POLL_CFG_GDSCR) {  in gdsc_check_status()
93 	return -EINVAL;  in gdsc_check_status()
100 	return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);  in gdsc_hwctrl()
116 	return -ETIMEDOUT;  in gdsc_poll_status()
124 	if (sc->collapse_mask) {  in gdsc_update_collapse_bit()
125 		reg = sc->collapse_ctrl;  in gdsc_update_collapse_bit()
126 		mask = sc->collapse_mask;  in gdsc_update_collapse_bit()
128 		reg = sc->gdscr;  in gdsc_update_collapse_bit()
132 	ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0);  in gdsc_update_collapse_bit()
144 	if (status == GDSC_ON && sc->rsupply) {  in gdsc_toggle_logic()
145 		ret = regulator_enable(sc->rsupply);  in gdsc_toggle_logic()
153 	if ((sc->flags & VOTABLE) && status == GDSC_OFF && !wait) {  in gdsc_toggle_logic()
163 	if (sc->gds_hw_ctrl) {  in gdsc_toggle_logic()
165 		 * The gds hw controller asserts/de-asserts the status bit soon  in gdsc_toggle_logic()
178 	WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");  in gdsc_toggle_logic()
180 	if (!ret && status == GDSC_OFF && sc->rsupply) {  in gdsc_toggle_logic()
181 		ret = regulator_disable(sc->rsupply);  in gdsc_toggle_logic()
193 	for (i = 0; i < sc->reset_count; i++)  in gdsc_deassert_reset()
194 		sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);  in gdsc_deassert_reset()
202 	for (i = 0; i < sc->reset_count; i++)  in gdsc_assert_reset()
203 		sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);  in gdsc_assert_reset()
212 	if (!(sc->flags & NO_RET_PERIPH))  in gdsc_force_mem_on()
215 	for (i = 0; i < sc->cxc_count; i++)  in gdsc_force_mem_on()
216 		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);  in gdsc_force_mem_on()
224 	if (!(sc->flags & NO_RET_PERIPH))  in gdsc_clear_mem_on()
227 	for (i = 0; i < sc->cxc_count; i++)  in gdsc_clear_mem_on()
228 		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);  in gdsc_clear_mem_on()
233 	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,  in gdsc_deassert_clamp_io()
239 	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,  in gdsc_assert_clamp_io()
245 	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,  in gdsc_assert_reset_aon()
248 	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,  in gdsc_assert_reset_aon()
256 	regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);  in gdsc_retain_ff_on()
264 	if (sc->pwrsts == PWRSTS_ON)  in gdsc_enable()
267 	if (sc->flags & SW_RESET) {  in gdsc_enable()
273 	if (sc->flags & CLAMP_IO) {  in gdsc_enable()
274 		if (sc->flags & AON_RESET)  in gdsc_enable()
283 	if (sc->pwrsts & PWRSTS_OFF)  in gdsc_enable()
288 	 * additional 4 clock cycles to re-enable after the power domain is  in gdsc_enable()
296 	if (sc->flags & HW_CTRL) {  in gdsc_enable()
311 	if (sc->flags & RETAIN_FF_ENABLE)  in gdsc_enable()
322 	if (sc->pwrsts == PWRSTS_ON)  in gdsc_disable()
326 	if (sc->flags & HW_CTRL) {  in gdsc_disable()
343 	if (sc->pwrsts & PWRSTS_OFF)  in gdsc_disable()
353 	if (sc->pwrsts == PWRSTS_RET_ON)  in gdsc_disable()
356 	ret = gdsc_toggle_logic(sc, GDSC_OFF, domain->synced_poweroff);  in gdsc_disable()
360 	if (sc->flags & CLAMP_IO)  in gdsc_disable()
372 	 * Disable HW trigger: collapse/restore occur based on registers writes.  in gdsc_init()
373 	 * Disable SW override: Use hardware state-machine for sequencing.  in gdsc_init()
379 	if (!sc->en_rest_wait_val)  in gdsc_init()
380 		sc->en_rest_wait_val = EN_REST_WAIT_VAL;  in gdsc_init()
381 	if (!sc->en_few_wait_val)  in gdsc_init()
382 		sc->en_few_wait_val = EN_FEW_WAIT_VAL;  in gdsc_init()
383 	if (!sc->clk_dis_wait_val)  in gdsc_init()
384 		sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL;  in gdsc_init()
386 	val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT |  in gdsc_init()
387 		sc->en_few_wait_val << EN_FEW_WAIT_SHIFT |  in gdsc_init()
388 		sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;  in gdsc_init()
390 	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);  in gdsc_init()
395 	if (sc->pwrsts == PWRSTS_ON) {  in gdsc_init()
407 		if (sc->rsupply) {  in gdsc_init()
408 			ret = regulator_enable(sc->rsupply);  in gdsc_init()
417 		if (sc->flags & VOTABLE) {  in gdsc_init()
424 		if (sc->flags & HW_CTRL) {  in gdsc_init()
435 		if (sc->flags & RETAIN_FF_ENABLE)  in gdsc_init()
437 	} else if (sc->flags & ALWAYS_ON) {  in gdsc_init()
439 		gdsc_enable(&sc->pd);  in gdsc_init()
443 	if (on || (sc->pwrsts & PWRSTS_RET))  in gdsc_init()
448 	if (sc->flags & ALWAYS_ON)  in gdsc_init()
449 		sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;  in gdsc_init()
450 	if (!sc->pd.power_off)  in gdsc_init()
451 		sc->pd.power_off = gdsc_disable;  in gdsc_init()
452 	if (!sc->pd.power_on)  in gdsc_init()
453 		sc->pd.power_on = gdsc_enable;  in gdsc_init()
455 	ret = pm_genpd_init(&sc->pd, NULL, !on);  in gdsc_init()
462 	if (on && sc->rsupply)  in gdsc_init()
463 		regulator_disable(sc->rsupply);  in gdsc_init()
473 	struct device *dev = desc->dev;  in gdsc_register()
474 	struct gdsc **scs = desc->scs;  in gdsc_register()
475 	size_t num = desc->num;  in gdsc_register()
479 		return -ENOMEM;  in gdsc_register()
481 	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),  in gdsc_register()
483 	if (!data->domains)  in gdsc_register()
484 		return -ENOMEM;  in gdsc_register()
487 		if (!scs[i] || !scs[i]->supply)  in gdsc_register()
490 		scs[i]->rsupply = devm_regulator_get(dev, scs[i]->supply);  in gdsc_register()
491 		if (IS_ERR(scs[i]->rsupply))  in gdsc_register()
492 			return PTR_ERR(scs[i]->rsupply);  in gdsc_register()
495 	data->num_domains = num;  in gdsc_register()
499 		scs[i]->regmap = regmap;  in gdsc_register()
500 		scs[i]->rcdev = rcdev;  in gdsc_register()
504 		data->domains[i] = &scs[i]->pd;  in gdsc_register()
511 		if (scs[i]->parent)  in gdsc_register()
512 			pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);  in gdsc_register()
513 		else if (!IS_ERR_OR_NULL(dev->pm_domain))  in gdsc_register()
514 			pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);  in gdsc_register()
517 	return of_genpd_add_provider_onecell(dev->of_node, data);  in gdsc_register()
523 	struct device *dev = desc->dev;  in gdsc_unregister()
524 	struct gdsc **scs = desc->scs;  in gdsc_unregister()
525 	size_t num = desc->num;  in gdsc_unregister()
531 		if (scs[i]->parent)  in gdsc_unregister()
532 			pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);  in gdsc_unregister()
533 		else if (!IS_ERR_OR_NULL(dev->pm_domain))  in gdsc_unregister()
534 			pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);  in gdsc_unregister()
536 	of_genpd_del_provider(dev->of_node);  in gdsc_unregister()
546  * the device the CPU needs to disable the GX headswitch. There being no sane
550  * defining a GX gdsc with a dummy enable function and a "default" disable
556  * is *really* off - this gives us a semi standard way of doing what we need.