Lines Matching +full:0 +full:x33000
44 .offset = 0x0,
47 .enable_reg = 0x52018,
48 .enable_mask = BIT(0),
61 { 0x1, 2 },
66 .offset = 0x0,
83 .offset = 0x76000,
86 .enable_reg = 0x52018,
101 .offset = 0x1c000,
104 .enable_reg = 0x52018,
119 { P_BI_TCXO, 0 },
131 { P_BI_TCXO, 0 },
145 { P_BI_TCXO, 0 },
155 { P_BI_TCXO, 0 },
163 { P_BI_TCXO, 0 },
179 { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
189 { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
199 { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
209 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
219 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
229 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
239 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
249 { P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 },
259 .reg = 0x6b054,
273 .reg = 0x8d054,
287 .reg = 0x75058,
288 .shift = 0,
302 .reg = 0x750c8,
303 .shift = 0,
317 .reg = 0x75048,
318 .shift = 0,
332 .reg = 0x77058,
333 .shift = 0,
347 .reg = 0x770c8,
348 .shift = 0,
362 .reg = 0x77048,
363 .shift = 0,
377 .reg = 0xf060,
378 .shift = 0,
392 .reg = 0x10060,
393 .shift = 0,
407 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
408 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
409 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
414 .cmd_rcgr = 0x64004,
429 .cmd_rcgr = 0x65004,
444 .cmd_rcgr = 0x66004,
459 F(9600000, P_BI_TCXO, 2, 0, 0),
460 F(19200000, P_BI_TCXO, 1, 0, 0),
465 .cmd_rcgr = 0x6b058,
480 F(19200000, P_BI_TCXO, 1, 0, 0),
481 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
486 .cmd_rcgr = 0x6b03c,
487 .mnd_width = 0,
501 .cmd_rcgr = 0x8d058,
516 .cmd_rcgr = 0x8d03c,
517 .mnd_width = 0,
531 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
536 .cmd_rcgr = 0x33010,
537 .mnd_width = 0,
553 F(19200000, P_BI_TCXO, 1, 0, 0),
558 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
561 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
574 .cmd_rcgr = 0x17010,
591 .cmd_rcgr = 0x17140,
608 .cmd_rcgr = 0x17270,
625 .cmd_rcgr = 0x173a0,
642 .cmd_rcgr = 0x174d0,
659 .cmd_rcgr = 0x17600,
676 .cmd_rcgr = 0x17730,
693 .cmd_rcgr = 0x17860,
704 F(19200000, P_BI_TCXO, 1, 0, 0),
709 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
712 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
716 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
729 .cmd_rcgr = 0x18010,
746 .cmd_rcgr = 0x18140,
763 .cmd_rcgr = 0x18270,
780 .cmd_rcgr = 0x183a0,
797 .cmd_rcgr = 0x184d0,
814 .cmd_rcgr = 0x18600,
831 .cmd_rcgr = 0x1e010,
848 .cmd_rcgr = 0x1e140,
865 .cmd_rcgr = 0x1e270,
882 .cmd_rcgr = 0x1e3a0,
899 .cmd_rcgr = 0x1e4d0,
916 .cmd_rcgr = 0x1e600,
926 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
927 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
928 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
929 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
934 .cmd_rcgr = 0x1400c,
950 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
951 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
956 .cmd_rcgr = 0x1600c,
971 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
972 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
973 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
974 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
979 .cmd_rcgr = 0x75024,
994 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
995 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
996 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1001 .cmd_rcgr = 0x7506c,
1002 .mnd_width = 0,
1016 F(19200000, P_BI_TCXO, 1, 0, 0),
1021 .cmd_rcgr = 0x750a0,
1022 .mnd_width = 0,
1036 .cmd_rcgr = 0x75084,
1037 .mnd_width = 0,
1051 .cmd_rcgr = 0x77024,
1066 .cmd_rcgr = 0x7706c,
1067 .mnd_width = 0,
1081 .cmd_rcgr = 0x770a0,
1082 .mnd_width = 0,
1096 .cmd_rcgr = 0x77084,
1097 .mnd_width = 0,
1111 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1112 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1113 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1114 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1119 .cmd_rcgr = 0xf020,
1134 .cmd_rcgr = 0xf038,
1135 .mnd_width = 0,
1149 .cmd_rcgr = 0x10020,
1164 .cmd_rcgr = 0x10038,
1165 .mnd_width = 0,
1179 .cmd_rcgr = 0xf064,
1180 .mnd_width = 0,
1194 .cmd_rcgr = 0x10064,
1195 .mnd_width = 0,
1209 .reg = 0xf050,
1210 .shift = 0,
1224 .reg = 0x10050,
1225 .shift = 0,
1240 .halt_reg = 0x6b080,
1243 .enable_reg = 0x52000,
1254 .halt_reg = 0x8d084,
1257 .enable_reg = 0x52000,
1267 .halt_reg = 0x9000c,
1269 .hwcg_reg = 0x9000c,
1272 .enable_reg = 0x52000,
1282 .halt_reg = 0x750cc,
1284 .hwcg_reg = 0x750cc,
1287 .enable_reg = 0x750cc,
1288 .enable_mask = BIT(0),
1302 .halt_reg = 0x750cc,
1304 .hwcg_reg = 0x750cc,
1307 .enable_reg = 0x750cc,
1322 .halt_reg = 0x770cc,
1324 .hwcg_reg = 0x770cc,
1327 .enable_reg = 0x770cc,
1328 .enable_mask = BIT(0),
1342 .halt_reg = 0x770cc,
1344 .hwcg_reg = 0x770cc,
1347 .enable_reg = 0x770cc,
1362 .halt_reg = 0xf080,
1364 .hwcg_reg = 0xf080,
1367 .enable_reg = 0xf080,
1368 .enable_mask = BIT(0),
1382 .halt_reg = 0x10080,
1384 .hwcg_reg = 0x10080,
1387 .enable_reg = 0x10080,
1388 .enable_mask = BIT(0),
1402 .halt_reg = 0x38004,
1404 .hwcg_reg = 0x38004,
1407 .enable_reg = 0x52000,
1418 .halt_reg = 0x26010,
1420 .hwcg_reg = 0x26010,
1423 .enable_reg = 0x26010,
1424 .enable_mask = BIT(0),
1434 .halt_reg = 0x26014,
1436 .hwcg_reg = 0x26014,
1439 .enable_reg = 0x26014,
1440 .enable_mask = BIT(0),
1449 .halt_reg = 0xf07c,
1451 .hwcg_reg = 0xf07c,
1454 .enable_reg = 0xf07c,
1455 .enable_mask = BIT(0),
1469 .halt_reg = 0x1007c,
1471 .hwcg_reg = 0x1007c,
1474 .enable_reg = 0x1007c,
1475 .enable_mask = BIT(0),
1490 .halt_reg = 0x71154,
1492 .hwcg_reg = 0x71154,
1495 .enable_reg = 0x71154,
1496 .enable_mask = BIT(0),
1506 .halt_reg = 0x8d080,
1508 .hwcg_reg = 0x8d080,
1511 .enable_reg = 0x52000,
1522 .halt_reg = 0x2700c,
1524 .hwcg_reg = 0x2700c,
1527 .enable_reg = 0x2700c,
1528 .enable_mask = BIT(0),
1538 .halt_reg = 0x27014,
1540 .hwcg_reg = 0x27014,
1543 .enable_reg = 0x27014,
1544 .enable_mask = BIT(0),
1553 .halt_reg = 0x64000,
1556 .enable_reg = 0x64000,
1557 .enable_mask = BIT(0),
1571 .halt_reg = 0x65000,
1574 .enable_reg = 0x65000,
1575 .enable_mask = BIT(0),
1589 .halt_reg = 0x66000,
1592 .enable_reg = 0x66000,
1593 .enable_mask = BIT(0),
1610 .enable_reg = 0x52000,
1628 .enable_reg = 0x52000,
1643 .halt_reg = 0x8c014,
1646 .enable_reg = 0x8c014,
1647 .enable_mask = BIT(0),
1656 .halt_reg = 0x7100c,
1658 .hwcg_reg = 0x7100c,
1661 .enable_reg = 0x7100c,
1662 .enable_mask = BIT(0),
1671 .halt_reg = 0x71018,
1674 .enable_reg = 0x71018,
1675 .enable_mask = BIT(0),
1684 .halt_reg = 0x6b038,
1687 .enable_reg = 0x52000,
1702 .halt_reg = 0x8d038,
1705 .enable_reg = 0x52000,
1720 .halt_reg = 0x6b028,
1723 .enable_reg = 0x52008,
1738 .halt_reg = 0x6b024,
1740 .hwcg_reg = 0x6b024,
1743 .enable_reg = 0x52008,
1753 .halt_reg = 0x8c004,
1756 .enable_reg = 0x8c004,
1757 .enable_mask = BIT(0),
1767 .halt_reg = 0x6b01c,
1769 .hwcg_reg = 0x6b01c,
1772 .enable_reg = 0x52008,
1783 .halt_reg = 0x6b030,
1786 .enable_reg = 0x52008,
1801 .halt_reg = 0x6b014,
1803 .hwcg_reg = 0x6b014,
1806 .enable_reg = 0x52008,
1807 .enable_mask = BIT(0),
1816 .halt_reg = 0x6b010,
1819 .enable_reg = 0x52008,
1829 .halt_reg = 0x8d028,
1832 .enable_reg = 0x52000,
1847 .halt_reg = 0x8d024,
1849 .hwcg_reg = 0x8d024,
1852 .enable_reg = 0x52000,
1862 .halt_reg = 0x8c008,
1865 .enable_reg = 0x8c008,
1866 .enable_mask = BIT(0),
1876 .halt_reg = 0x8d01c,
1878 .hwcg_reg = 0x8d01c,
1881 .enable_reg = 0x52000,
1892 .halt_reg = 0x8d030,
1895 .enable_reg = 0x52000,
1910 .halt_reg = 0x8d014,
1912 .hwcg_reg = 0x8d014,
1915 .enable_reg = 0x52000,
1925 .halt_reg = 0x8d010,
1928 .enable_reg = 0x52000,
1938 .halt_reg = 0x3300c,
1941 .enable_reg = 0x3300c,
1942 .enable_mask = BIT(0),
1956 .halt_reg = 0x33004,
1958 .hwcg_reg = 0x33004,
1961 .enable_reg = 0x33004,
1962 .enable_mask = BIT(0),
1971 .halt_reg = 0x33008,
1974 .enable_reg = 0x33008,
1975 .enable_mask = BIT(0),
1984 .halt_reg = 0x26008,
1986 .hwcg_reg = 0x26008,
1989 .enable_reg = 0x26008,
1990 .enable_mask = BIT(0),
1999 .halt_reg = 0x2600c,
2001 .hwcg_reg = 0x2600c,
2004 .enable_reg = 0x2600c,
2005 .enable_mask = BIT(0),
2014 .halt_reg = 0x27008,
2016 .hwcg_reg = 0x27008,
2019 .enable_reg = 0x27008,
2020 .enable_mask = BIT(0),
2029 .halt_reg = 0x28008,
2031 .hwcg_reg = 0x28008,
2034 .enable_reg = 0x28008,
2035 .enable_mask = BIT(0),
2044 .halt_reg = 0x2800c,
2046 .hwcg_reg = 0x2800c,
2049 .enable_reg = 0x2800c,
2050 .enable_mask = BIT(0),
2059 .halt_reg = 0x23008,
2062 .enable_reg = 0x52008,
2072 .halt_reg = 0x23000,
2075 .enable_reg = 0x52008,
2085 .halt_reg = 0x1700c,
2088 .enable_reg = 0x52008,
2103 .halt_reg = 0x1713c,
2106 .enable_reg = 0x52008,
2121 .halt_reg = 0x1726c,
2124 .enable_reg = 0x52008,
2139 .halt_reg = 0x1739c,
2142 .enable_reg = 0x52008,
2157 .halt_reg = 0x174cc,
2160 .enable_reg = 0x52008,
2175 .halt_reg = 0x175fc,
2178 .enable_reg = 0x52008,
2193 .halt_reg = 0x1772c,
2196 .enable_reg = 0x52008,
2211 .halt_reg = 0x1785c,
2214 .enable_reg = 0x52008,
2229 .halt_reg = 0x23140,
2232 .enable_reg = 0x52008,
2242 .halt_reg = 0x23138,
2245 .enable_reg = 0x52008,
2255 .halt_reg = 0x18004,
2257 .hwcg_reg = 0x18004,
2260 .enable_reg = 0x52008,
2270 .halt_reg = 0x18008,
2272 .hwcg_reg = 0x18008,
2275 .enable_reg = 0x52008,
2285 .halt_reg = 0x1800c,
2288 .enable_reg = 0x52008,
2303 .halt_reg = 0x1813c,
2306 .enable_reg = 0x52008,
2321 .halt_reg = 0x1826c,
2324 .enable_reg = 0x52008,
2339 .halt_reg = 0x1839c,
2342 .enable_reg = 0x52008,
2357 .halt_reg = 0x184cc,
2360 .enable_reg = 0x52008,
2375 .halt_reg = 0x185fc,
2378 .enable_reg = 0x52008,
2393 .halt_reg = 0x23278,
2396 .enable_reg = 0x52010,
2406 .halt_reg = 0x23270,
2409 .enable_reg = 0x52010,
2410 .enable_mask = BIT(0),
2419 .halt_reg = 0x1e00c,
2422 .enable_reg = 0x52010,
2437 .halt_reg = 0x1e13c,
2440 .enable_reg = 0x52010,
2455 .halt_reg = 0x1e26c,
2458 .enable_reg = 0x52010,
2473 .halt_reg = 0x1e39c,
2476 .enable_reg = 0x52010,
2491 .halt_reg = 0x1e4cc,
2494 .enable_reg = 0x52010,
2509 .halt_reg = 0x1e5fc,
2512 .enable_reg = 0x52010,
2527 .halt_reg = 0x17004,
2529 .hwcg_reg = 0x17004,
2532 .enable_reg = 0x52008,
2542 .halt_reg = 0x17008,
2544 .hwcg_reg = 0x17008,
2547 .enable_reg = 0x52008,
2557 .halt_reg = 0x1e004,
2559 .hwcg_reg = 0x1e004,
2562 .enable_reg = 0x52010,
2572 .halt_reg = 0x1e008,
2574 .hwcg_reg = 0x1e008,
2577 .enable_reg = 0x52010,
2587 .halt_reg = 0x14008,
2590 .enable_reg = 0x14008,
2591 .enable_mask = BIT(0),
2600 .halt_reg = 0x14004,
2603 .enable_reg = 0x14004,
2604 .enable_mask = BIT(0),
2618 .halt_reg = 0x16008,
2621 .enable_reg = 0x16008,
2622 .enable_mask = BIT(0),
2631 .halt_reg = 0x16004,
2634 .enable_reg = 0x16004,
2635 .enable_mask = BIT(0),
2649 .halt_reg = 0x9044,
2652 .enable_reg = 0x9044,
2653 .enable_mask = BIT(0),
2662 .halt_reg = 0x8c000,
2665 .enable_reg = 0x8c000,
2666 .enable_mask = BIT(0),
2675 .halt_reg = 0x75018,
2677 .hwcg_reg = 0x75018,
2680 .enable_reg = 0x75018,
2681 .enable_mask = BIT(0),
2690 .halt_reg = 0x75010,
2692 .hwcg_reg = 0x75010,
2695 .enable_reg = 0x75010,
2696 .enable_mask = BIT(0),
2710 .halt_reg = 0x75010,
2712 .hwcg_reg = 0x75010,
2715 .enable_reg = 0x75010,
2730 .halt_reg = 0x75064,
2732 .hwcg_reg = 0x75064,
2735 .enable_reg = 0x75064,
2736 .enable_mask = BIT(0),
2750 .halt_reg = 0x75064,
2752 .hwcg_reg = 0x75064,
2755 .enable_reg = 0x75064,
2770 .halt_reg = 0x7509c,
2772 .hwcg_reg = 0x7509c,
2775 .enable_reg = 0x7509c,
2776 .enable_mask = BIT(0),
2790 .halt_reg = 0x7509c,
2792 .hwcg_reg = 0x7509c,
2795 .enable_reg = 0x7509c,
2811 .halt_reg = 0x75020,
2814 .enable_reg = 0x75020,
2815 .enable_mask = BIT(0),
2830 .halt_reg = 0x750b8,
2833 .enable_reg = 0x750b8,
2834 .enable_mask = BIT(0),
2849 .halt_reg = 0x7501c,
2852 .enable_reg = 0x7501c,
2853 .enable_mask = BIT(0),
2867 .halt_reg = 0x7505c,
2869 .hwcg_reg = 0x7505c,
2872 .enable_reg = 0x7505c,
2873 .enable_mask = BIT(0),
2887 .halt_reg = 0x7505c,
2889 .hwcg_reg = 0x7505c,
2892 .enable_reg = 0x7505c,
2907 .halt_reg = 0x77018,
2909 .hwcg_reg = 0x77018,
2912 .enable_reg = 0x77018,
2913 .enable_mask = BIT(0),
2922 .halt_reg = 0x77010,
2924 .hwcg_reg = 0x77010,
2927 .enable_reg = 0x77010,
2928 .enable_mask = BIT(0),
2942 .halt_reg = 0x77010,
2944 .hwcg_reg = 0x77010,
2947 .enable_reg = 0x77010,
2962 .halt_reg = 0x77064,
2964 .hwcg_reg = 0x77064,
2967 .enable_reg = 0x77064,
2968 .enable_mask = BIT(0),
2982 .halt_reg = 0x77064,
2984 .hwcg_reg = 0x77064,
2987 .enable_reg = 0x77064,
3002 .halt_reg = 0x7709c,
3004 .hwcg_reg = 0x7709c,
3007 .enable_reg = 0x7709c,
3008 .enable_mask = BIT(0),
3022 .halt_reg = 0x7709c,
3024 .hwcg_reg = 0x7709c,
3027 .enable_reg = 0x7709c,
3043 .halt_reg = 0x77020,
3046 .enable_reg = 0x77020,
3047 .enable_mask = BIT(0),
3062 .halt_reg = 0x770b8,
3065 .enable_reg = 0x770b8,
3066 .enable_mask = BIT(0),
3081 .halt_reg = 0x7701c,
3084 .enable_reg = 0x7701c,
3085 .enable_mask = BIT(0),
3099 .halt_reg = 0x7705c,
3101 .hwcg_reg = 0x7705c,
3104 .enable_reg = 0x7705c,
3105 .enable_mask = BIT(0),
3119 .halt_reg = 0x7705c,
3121 .hwcg_reg = 0x7705c,
3124 .enable_reg = 0x7705c,
3139 .halt_reg = 0xf010,
3142 .enable_reg = 0xf010,
3143 .enable_mask = BIT(0),
3157 .halt_reg = 0xf010,
3160 .enable_reg = 0xf010,
3170 .halt_reg = 0xf01c,
3173 .enable_reg = 0xf01c,
3174 .enable_mask = BIT(0),
3188 .halt_reg = 0xf018,
3191 .enable_reg = 0xf018,
3192 .enable_mask = BIT(0),
3201 .halt_reg = 0x10010,
3204 .enable_reg = 0x10010,
3205 .enable_mask = BIT(0),
3219 .halt_reg = 0x10010,
3222 .enable_reg = 0x10010,
3232 .halt_reg = 0x1001c,
3235 .enable_reg = 0x1001c,
3236 .enable_mask = BIT(0),
3250 .halt_reg = 0x10018,
3253 .enable_reg = 0x10018,
3254 .enable_mask = BIT(0),
3263 .halt_reg = 0xf054,
3266 .enable_reg = 0xf054,
3267 .enable_mask = BIT(0),
3281 .halt_reg = 0xf058,
3284 .enable_reg = 0xf058,
3285 .enable_mask = BIT(0),
3300 .halt_reg = 0xf05c,
3302 .hwcg_reg = 0xf05c,
3305 .enable_reg = 0xf05c,
3306 .enable_mask = BIT(0),
3320 .halt_reg = 0x8c010,
3323 .enable_reg = 0x8c010,
3324 .enable_mask = BIT(0),
3333 .halt_reg = 0x10054,
3336 .enable_reg = 0x10054,
3337 .enable_mask = BIT(0),
3351 .halt_reg = 0x10058,
3354 .enable_reg = 0x10058,
3355 .enable_mask = BIT(0),
3370 .halt_reg = 0x1005c,
3373 .enable_reg = 0x1005c,
3374 .enable_mask = BIT(0),
3389 .halt_reg = 0x28010,
3391 .hwcg_reg = 0x28010,
3394 .enable_reg = 0x28010,
3395 .enable_mask = BIT(0),
3405 .halt_reg = 0x28018,
3407 .hwcg_reg = 0x28018,
3410 .enable_reg = 0x28018,
3411 .enable_mask = BIT(0),
3420 .gdscr = 0x6b004,
3428 .gdscr = 0x8d004,
3436 .gdscr = 0x75004,
3444 .gdscr = 0x77004,
3452 .gdscr = 0xf004,
3460 .gdscr = 0x10004,
3468 .gdscr = 0x7d050,
3477 .gdscr = 0x7d058,
3486 .gdscr = 0x7d054,
3495 .gdscr = 0x7d06c,
3711 [GCC_CAMERA_BCR] = { 0x26000 },
3712 [GCC_DISPLAY_BCR] = { 0x27000 },
3713 [GCC_GPU_BCR] = { 0x71000 },
3714 [GCC_MMSS_BCR] = { 0xb000 },
3715 [GCC_PCIE_0_BCR] = { 0x6b000 },
3716 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3717 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3718 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3719 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3720 [GCC_PCIE_1_BCR] = { 0x8d000 },
3721 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3722 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3723 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3724 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
3725 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3726 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3727 [GCC_PDM_BCR] = { 0x33000 },
3728 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3729 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3730 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3731 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3732 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3733 [GCC_SDCC2_BCR] = { 0x14000 },
3734 [GCC_SDCC4_BCR] = { 0x16000 },
3735 [GCC_UFS_CARD_BCR] = { 0x75000 },
3736 [GCC_UFS_PHY_BCR] = { 0x77000 },
3737 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3738 [GCC_USB30_SEC_BCR] = { 0x10000 },
3739 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3740 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3741 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3742 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3743 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3744 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3745 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3746 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
3747 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
3748 [GCC_VIDEO_BCR] = { 0x28000 },
3778 .max_register = 0x9c100,
3814 regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); in gcc_sm8350_probe()
3815 regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0)); in gcc_sm8350_probe()
3816 regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); in gcc_sm8350_probe()
3817 regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0)); in gcc_sm8350_probe()
3818 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); in gcc_sm8350_probe()
3819 regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); in gcc_sm8350_probe()
3820 regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0)); in gcc_sm8350_probe()