Lines Matching +full:0 +full:x37000
35 .offset = 0x0,
38 .enable_reg = 0x52010,
39 .enable_mask = BIT(0),
52 { 0x1, 2 },
57 .offset = 0x0,
74 { 0x3, 3 },
79 .offset = 0x0,
96 .offset = 0x6000,
99 .enable_reg = 0x52010,
113 { 0x1, 2 },
118 .offset = 0x6000,
135 .offset = 0x7000,
138 .enable_reg = 0x52010,
152 { P_BI_TCXO, 0 },
166 { P_BI_TCXO, 0 },
176 { P_BI_TCXO, 0 },
186 { P_BI_TCXO, 0 },
194 { P_BI_TCXO, 0 },
206 { P_BI_TCXO, 0 },
220 { P_BI_TCXO, 0 },
230 { P_BI_TCXO, 0 },
242 { P_BI_TCXO, 0 },
254 .reg = 0x4514C,
255 .shift = 0,
268 .reg = 0x4ce00,
269 .shift = 0,
282 F(19200000, P_BI_TCXO, 1, 0, 0),
287 .cmd_rcgr = 0x30014,
288 .mnd_width = 0,
301 F(19200000, P_BI_TCXO, 1, 0, 0),
302 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
303 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
304 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
305 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
310 .cmd_rcgr = 0x37004,
324 .cmd_rcgr = 0x38004,
338 .cmd_rcgr = 0x39004,
352 F(19200000, P_BI_TCXO, 1, 0, 0),
353 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
358 .cmd_rcgr = 0x23010,
359 .mnd_width = 0,
374 F(19200000, P_BI_TCXO, 1, 0, 0),
379 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
382 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
386 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
387 F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0),
399 .cmd_rcgr = 0x21148,
415 .cmd_rcgr = 0x21278,
431 .cmd_rcgr = 0x213a8,
447 .cmd_rcgr = 0x214d8,
463 .cmd_rcgr = 0x21608,
479 .cmd_rcgr = 0x21738,
495 .cmd_rcgr = 0x22018,
511 .cmd_rcgr = 0x22148,
527 .cmd_rcgr = 0x22278,
543 .cmd_rcgr = 0x223a8,
559 .cmd_rcgr = 0x224d8,
575 .cmd_rcgr = 0x22608,
586 F(19200000, P_BI_TCXO, 1, 0, 0),
588 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
589 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
590 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
591 F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0),
592 F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
597 .cmd_rcgr = 0x4b024,
611 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
612 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
613 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
618 .cmd_rcgr = 0x4b00c,
619 .mnd_width = 0,
633 F(9600000, P_BI_TCXO, 2, 0, 0),
634 F(19200000, P_BI_TCXO, 1, 0, 0),
635 F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
636 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
637 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
638 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
643 .cmd_rcgr = 0x2000c,
658 F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
659 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
660 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
661 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
662 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
667 .cmd_rcgr = 0x3a01c,
681 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
682 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
683 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
684 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
689 .cmd_rcgr = 0x3a048,
690 .mnd_width = 0,
703 F(9600000, P_BI_TCXO, 2, 0, 0),
704 F(19200000, P_BI_TCXO, 1, 0, 0),
709 .cmd_rcgr = 0x3a0b0,
710 .mnd_width = 0,
723 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
724 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
725 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
730 .cmd_rcgr = 0x3a060,
731 .mnd_width = 0,
744 F(66666667, P_GPLL0_OUT_ODD, 3, 0, 0),
745 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
746 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
747 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
752 .cmd_rcgr = 0x1a01c,
766 F(19200000, P_BI_TCXO, 1, 0, 0),
771 .cmd_rcgr = 0x1a034,
772 .mnd_width = 0,
785 .cmd_rcgr = 0x1a060,
786 .mnd_width = 0,
799 .halt_reg = 0x3e014,
801 .hwcg_reg = 0x3e014,
804 .enable_reg = 0x3e014,
805 .enable_mask = BIT(0),
819 .halt_reg = 0x3e014,
821 .hwcg_reg = 0x3e014,
824 .enable_reg = 0x3e014,
839 .halt_reg = 0x3e014,
841 .hwcg_reg = 0x3e014,
844 .enable_reg = 0x3e014,
859 .halt_reg = 0x3e010,
861 .hwcg_reg = 0x3e010,
864 .enable_reg = 0x3e010,
865 .enable_mask = BIT(0),
879 .halt_reg = 0x26004,
881 .hwcg_reg = 0x26004,
884 .enable_reg = 0x52000,
894 .halt_reg = 0x17008,
896 .hwcg_reg = 0x17008,
899 .enable_reg = 0x17008,
900 .enable_mask = BIT(0),
910 .halt_reg = 0x17018,
912 .hwcg_reg = 0x17018,
915 .enable_reg = 0x17018,
916 .enable_mask = BIT(0),
925 .halt_reg = 0x17078,
927 .hwcg_reg = 0x17078,
930 .enable_reg = 0x17078,
931 .enable_mask = BIT(0),
940 .halt_reg = 0x17024,
942 .hwcg_reg = 0x17024,
945 .enable_reg = 0x17024,
946 .enable_mask = BIT(0),
955 .halt_reg = 0x17030,
958 .enable_reg = 0x17030,
959 .enable_mask = BIT(0),
969 .halt_reg = 0x2b00c,
971 .hwcg_reg = 0x2b00c,
974 .enable_reg = 0x52008,
984 .halt_reg = 0x2b008,
987 .enable_reg = 0x52008,
997 .halt_reg = 0x2b004,
1000 .enable_reg = 0x52008,
1010 .halt_reg = 0x1101c,
1012 .hwcg_reg = 0x1101c,
1015 .enable_reg = 0x1101c,
1016 .enable_mask = BIT(0),
1030 .halt_reg = 0x30000,
1032 .hwcg_reg = 0x30000,
1035 .enable_reg = 0x52008,
1050 .halt_reg = 0x30004,
1052 .hwcg_reg = 0x30004,
1055 .enable_reg = 0x52008,
1066 .halt_reg = 0x30008,
1069 .enable_reg = 0x30008,
1070 .enable_mask = BIT(0),
1079 .halt_reg = 0x2d038,
1081 .hwcg_reg = 0x2d038,
1084 .enable_reg = 0x2d038,
1085 .enable_mask = BIT(0),
1094 .halt_reg = 0x1700c,
1096 .hwcg_reg = 0x1700c,
1099 .enable_reg = 0x1700c,
1100 .enable_mask = BIT(0),
1110 .halt_reg = 0x1701c,
1112 .hwcg_reg = 0x1701c,
1115 .enable_reg = 0x1701c,
1116 .enable_mask = BIT(0),
1125 .halt_reg = 0x17074,
1127 .hwcg_reg = 0x17074,
1130 .enable_reg = 0x17074,
1131 .enable_mask = BIT(0),
1140 .halt_reg = 0x17070,
1142 .hwcg_reg = 0x17070,
1145 .enable_reg = 0x17070,
1146 .enable_mask = BIT(0),
1158 .enable_reg = 0x52000,
1172 .halt_reg = 0x17028,
1174 .hwcg_reg = 0x17028,
1177 .enable_reg = 0x17028,
1178 .enable_mask = BIT(0),
1187 .halt_reg = 0x17034,
1190 .enable_reg = 0x17034,
1191 .enable_mask = BIT(0),
1200 .halt_reg = 0x37000,
1203 .enable_reg = 0x37000,
1204 .enable_mask = BIT(0),
1218 .halt_reg = 0x38000,
1221 .enable_reg = 0x38000,
1222 .enable_mask = BIT(0),
1236 .halt_reg = 0x39000,
1239 .enable_reg = 0x39000,
1240 .enable_mask = BIT(0),
1254 .halt_reg = 0x45004,
1256 .hwcg_reg = 0x45004,
1259 .enable_reg = 0x45004,
1260 .enable_mask = BIT(0),
1272 .enable_reg = 0x52008,
1288 .enable_reg = 0x52008,
1302 .halt_reg = 0x4500c,
1304 .hwcg_reg = 0x4500c,
1307 .enable_reg = 0x4500c,
1308 .enable_mask = BIT(0),
1317 .halt_reg = 0x45014,
1319 .hwcg_reg = 0x45014,
1322 .enable_reg = 0x45014,
1323 .enable_mask = BIT(0),
1332 .halt_reg = 0x4c008,
1334 .hwcg_reg = 0x4c008,
1337 .enable_reg = 0x4c008,
1338 .enable_mask = BIT(0),
1347 .halt_reg = 0x4d004,
1349 .hwcg_reg = 0x4d004,
1352 .enable_reg = 0x4d004,
1353 .enable_mask = BIT(0),
1362 .halt_reg = 0x4d008,
1365 .enable_reg = 0x4d008,
1366 .enable_mask = BIT(0),
1375 .halt_reg = 0x4d00c,
1378 .enable_reg = 0x4d00c,
1379 .enable_mask = BIT(0),
1388 .halt_reg = 0x4c004,
1390 .hwcg_reg = 0x4c004,
1393 .enable_reg = 0x4c004,
1394 .enable_mask = BIT(0),
1404 .halt_reg = 0x4c140,
1406 .hwcg_reg = 0x4c140,
1409 .enable_reg = 0x4c140,
1410 .enable_mask = BIT(0),
1421 .enable_reg = 0x52008,
1437 .enable_reg = 0x52008,
1451 .halt_reg = 0x2300c,
1454 .enable_reg = 0x2300c,
1455 .enable_mask = BIT(0),
1469 .halt_reg = 0x23004,
1471 .hwcg_reg = 0x23004,
1474 .enable_reg = 0x23004,
1475 .enable_mask = BIT(0),
1484 .halt_reg = 0x23008,
1487 .enable_reg = 0x23008,
1488 .enable_mask = BIT(0),
1497 .halt_reg = 0x24004,
1499 .hwcg_reg = 0x24004,
1502 .enable_reg = 0x52000,
1512 .halt_reg = 0x21014,
1515 .enable_reg = 0x52000,
1525 .halt_reg = 0x2100c,
1528 .enable_reg = 0x52000,
1538 .halt_reg = 0x21144,
1541 .enable_reg = 0x52000,
1556 .halt_reg = 0x21274,
1559 .enable_reg = 0x52000,
1574 .halt_reg = 0x213a4,
1577 .enable_reg = 0x52000,
1592 .halt_reg = 0x214d4,
1595 .enable_reg = 0x52000,
1610 .halt_reg = 0x21604,
1613 .enable_reg = 0x52000,
1628 .halt_reg = 0x21734,
1631 .enable_reg = 0x52000,
1646 .halt_reg = 0x22004,
1649 .enable_reg = 0x52000,
1659 .halt_reg = 0x22008,
1662 .enable_reg = 0x52000,
1672 .halt_reg = 0x22014,
1675 .enable_reg = 0x52000,
1690 .halt_reg = 0x22144,
1693 .enable_reg = 0x52000,
1708 .halt_reg = 0x22274,
1711 .enable_reg = 0x52000,
1726 .halt_reg = 0x223a4,
1729 .enable_reg = 0x52000,
1744 .halt_reg = 0x224d4,
1747 .enable_reg = 0x52000,
1762 .halt_reg = 0x22604,
1765 .enable_reg = 0x52000,
1780 .halt_reg = 0x21004,
1782 .hwcg_reg = 0x21004,
1785 .enable_reg = 0x52000,
1795 .halt_reg = 0x21008,
1797 .hwcg_reg = 0x21008,
1800 .enable_reg = 0x52000,
1810 .halt_reg = 0x2200c,
1812 .hwcg_reg = 0x2200c,
1815 .enable_reg = 0x52000,
1825 .halt_reg = 0x22010,
1827 .hwcg_reg = 0x22010,
1830 .enable_reg = 0x52000,
1840 .halt_reg = 0x4b004,
1843 .enable_reg = 0x4b004,
1844 .enable_mask = BIT(0),
1853 .halt_reg = 0x4b008,
1856 .enable_reg = 0x4b008,
1857 .enable_mask = BIT(0),
1871 .halt_reg = 0x4b03c,
1873 .hwcg_reg = 0x4b03c,
1876 .enable_reg = 0x4b03c,
1877 .enable_mask = BIT(0),
1891 .halt_reg = 0x20008,
1894 .enable_reg = 0x20008,
1895 .enable_mask = BIT(0),
1904 .halt_reg = 0x20004,
1907 .enable_reg = 0x20004,
1908 .enable_mask = BIT(0),
1922 .halt_reg = 0x10140,
1924 .hwcg_reg = 0x10140,
1927 .enable_reg = 0x52000,
1928 .enable_mask = BIT(0),
1942 .halt_reg = 0x8c000,
1945 .enable_reg = 0x8c000,
1946 .enable_mask = BIT(0),
1955 .halt_reg = 0x3a00c,
1957 .hwcg_reg = 0x3a00c,
1960 .enable_reg = 0x3a00c,
1961 .enable_mask = BIT(0),
1970 .halt_reg = 0x3a034,
1972 .hwcg_reg = 0x3a034,
1975 .enable_reg = 0x3a034,
1976 .enable_mask = BIT(0),
1990 .halt_reg = 0x3a0a4,
1992 .hwcg_reg = 0x3a0a4,
1995 .enable_reg = 0x3a0a4,
1996 .enable_mask = BIT(0),
2010 .halt_reg = 0x3a0a4,
2012 .hwcg_reg = 0x3a0a4,
2015 .enable_reg = 0x3a0a4,
2030 .halt_reg = 0x3a0ac,
2032 .hwcg_reg = 0x3a0ac,
2035 .enable_reg = 0x3a0ac,
2036 .enable_mask = BIT(0),
2050 .halt_reg = 0x3a0ac,
2052 .hwcg_reg = 0x3a0ac,
2055 .enable_reg = 0x3a0ac,
2070 .halt_reg = 0x3a014,
2073 .enable_reg = 0x3a014,
2074 .enable_mask = BIT(0),
2083 .halt_reg = 0x3a018,
2086 .enable_reg = 0x3a018,
2087 .enable_mask = BIT(0),
2096 .halt_reg = 0x3a010,
2099 .enable_reg = 0x3a010,
2100 .enable_mask = BIT(0),
2109 .halt_reg = 0x3a09c,
2111 .hwcg_reg = 0x3a09c,
2114 .enable_reg = 0x3a09c,
2115 .enable_mask = BIT(0),
2129 .halt_reg = 0x3a09c,
2131 .hwcg_reg = 0x3a09c,
2134 .enable_reg = 0x3a09c,
2149 .halt_reg = 0x1a00c,
2152 .enable_reg = 0x1a00c,
2153 .enable_mask = BIT(0),
2167 .halt_reg = 0x1a018,
2170 .enable_reg = 0x1a018,
2171 .enable_mask = BIT(0),
2185 .halt_reg = 0x1a014,
2188 .enable_reg = 0x1a014,
2189 .enable_mask = BIT(0),
2198 .halt_reg = 0x8c010,
2201 .enable_reg = 0x8c010,
2202 .enable_mask = BIT(0),
2211 .halt_reg = 0x1a050,
2214 .enable_reg = 0x1a050,
2215 .enable_mask = BIT(0),
2229 .halt_reg = 0x1a054,
2232 .enable_reg = 0x1a054,
2233 .enable_mask = BIT(0),
2247 .halt_reg = 0x1a058,
2249 .hwcg_reg = 0x1a058,
2252 .enable_reg = 0x1a058,
2253 .enable_mask = BIT(0),
2262 .halt_reg = 0x17004,
2264 .hwcg_reg = 0x17004,
2267 .enable_reg = 0x17004,
2268 .enable_mask = BIT(0),
2278 .halt_reg = 0x17014,
2280 .hwcg_reg = 0x17014,
2283 .enable_reg = 0x17014,
2284 .enable_mask = BIT(0),
2293 .halt_reg = 0x17020,
2295 .hwcg_reg = 0x17020,
2298 .enable_reg = 0x17020,
2299 .enable_mask = BIT(0),
2308 .halt_reg = 0x1702c,
2311 .enable_reg = 0x1702c,
2312 .enable_mask = BIT(0),
2322 .gdscr = 0x1a004,
2330 .gdscr = 0x3a004,
2338 .gdscr = 0xb7040,
2347 .gdscr = 0xb7044,
2501 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1d000 },
2502 [GCC_QUSB2PHY_SEC_BCR] = { 0x1e000 },
2503 [GCC_SDCC1_BCR] = { 0x4b000 },
2504 [GCC_SDCC2_BCR] = { 0x20000 },
2505 [GCC_UFS_PHY_BCR] = { 0x3a000 },
2506 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
2507 [GCC_USB3_PHY_PRIM_BCR] = { 0x1c000 },
2508 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1c008 },
2530 .max_register = 0xbf030,
2560 regmap_update_bits(regmap, 0x4cf00, 0x3, 0x3); in gcc_sm6350_probe()
2561 regmap_update_bits(regmap, 0x45f00, 0x3, 0x3); in gcc_sm6350_probe()