clk/qcom/gcc-sdm845.c

44 			.name = "gpll0",
46 				.fw_name = "bi_tcxo", .name = "bi_tcxo",
61 			.name = "gpll4",
63 				.fw_name = "bi_tcxo", .name = "bi_tcxo",
78 			.name = "gpll6",
80 				.fw_name = "bi_tcxo", .name = "bi_tcxo",
104 		.name = "gpll0_out_even",
120 	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
133 	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
135 	{ .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },
145 	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
146 	{ .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },
155 	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
164 	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
175 	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
177 	{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
182 	{ .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
185 	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
189 	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
191 	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
195 	{ .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
197 	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
208 	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
222 	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
240 		.name = "gcc_cpuss_ahb_clk_src",
259 		.name = "gcc_cpuss_rbcpr_clk_src",
279 		.name = "gcc_cpuss_rbcpr_clk_src",
302 		.name = "gcc_gp1_clk_src",
316 		.name = "gcc_gp2_clk_src",
330 		.name = "gcc_gp3_clk_src",
350 		.name = "gcc_pcie_0_aux_clk_src",
364 		.name = "gcc_pcie_1_aux_clk_src",
384 		.name = "gcc_pcie_phy_refgen_clk_src",
406 		.name = "gcc_qspi_core_clk_src",
427 		.name = "gcc_pdm2_clk_src",
454 	.name = "gcc_qupv3_wrap0_s0_clk_src",
470 	.name = "gcc_qupv3_wrap0_s1_clk_src",
486 	.name = "gcc_qupv3_wrap0_s2_clk_src",
502 	.name = "gcc_qupv3_wrap0_s3_clk_src",
518 	.name = "gcc_qupv3_wrap0_s4_clk_src",
534 	.name = "gcc_qupv3_wrap0_s5_clk_src",
550 	.name = "gcc_qupv3_wrap0_s6_clk_src",
566 	.name = "gcc_qupv3_wrap0_s7_clk_src",
582 	.name = "gcc_qupv3_wrap1_s0_clk_src",
598 	.name = "gcc_qupv3_wrap1_s1_clk_src",
614 	.name = "gcc_qupv3_wrap1_s2_clk_src",
630 	.name = "gcc_qupv3_wrap1_s3_clk_src",
646 	.name = "gcc_qupv3_wrap1_s4_clk_src",
662 	.name = "gcc_qupv3_wrap1_s5_clk_src",
678 	.name = "gcc_qupv3_wrap1_s6_clk_src",
694 	.name = "gcc_qupv3_wrap1_s7_clk_src",
728 		.name = "gcc_sdcc1_apps_clk_src",
750 		.name = "gcc_sdcc1_ice_core_clk_src",
775 		.name = "gcc_sdcc2_apps_clk_src",
799 		.name = "gcc_sdcc4_apps_clk_src",
824 		.name = "gcc_sdcc4_apps_clk_src",
843 		.name = "gcc_tsif_ref_clk_src",
866 		.name = "gcc_ufs_card_axi_clk_src",
888 		.name = "gcc_ufs_card_ice_core_clk_src",
902 		.name = "gcc_ufs_card_phy_aux_clk_src",
923 		.name = "gcc_ufs_card_unipro_core_clk_src",
946 		.name = "gcc_ufs_phy_axi_clk_src",
960 		.name = "gcc_ufs_phy_ice_core_clk_src",
974 		.name = "gcc_ufs_phy_phy_aux_clk_src",
988 		.name = "gcc_ufs_phy_unipro_core_clk_src",
1011 		.name = "gcc_usb30_prim_master_clk_src",
1033 		.name = "gcc_usb30_prim_mock_utmi_clk_src",
1047 		.name = "gcc_usb30_sec_master_clk_src",
1061 		.name = "gcc_usb30_sec_mock_utmi_clk_src",
1075 		.name = "gcc_usb3_prim_phy_aux_clk_src",
1089 		.name = "gcc_usb3_sec_phy_aux_clk_src",
1103 		.name = "gcc_vs_ctrl_clk_src",
1124 		.name = "gcc_vsensor_clk_src",
1138 			.name = "gcc_aggre_noc_pcie_tbu_clk",
1153 			.name = "gcc_aggre_ufs_card_axi_clk",
1173 			.name = "gcc_aggre_ufs_phy_axi_clk",
1191 			.name = "gcc_aggre_usb3_prim_axi_clk",
1209 			.name = "gcc_aggre_usb3_sec_axi_clk",
1227 			.name = "gcc_apc_vs_clk",
1247 			.name = "gcc_boot_rom_ahb_clk",
1262 			.name = "gcc_camera_ahb_clk",
1276 			.name = "gcc_camera_axi_clk",
1289 			.name = "gcc_camera_xo_clk",
1305 			.name = "gcc_ce1_ahb_clk",
1318 			.name = "gcc_ce1_axi_clk",
1331 			.name = "gcc_ce1_clk",
1344 			.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1362 			.name = "gcc_cfg_noc_usb3_sec_axi_clk",
1380 			.name = "gcc_cpuss_ahb_clk",
1398 			.name = "gcc_cpuss_rbcpr_clk",
1420 			.name = "gcc_cpuss_rbcpr_clk",
1438 			.name = "gcc_ddrss_gpu_axi_clk",
1453 			.name = "gcc_disp_ahb_clk",
1467 			.name = "gcc_disp_axi_clk",
1479 			.name = "gcc_disp_gpll0_clk_src",
1495 			.name = "gcc_disp_gpll0_div_clk_src",
1512 			.name = "gcc_disp_xo_clk",
1526 			.name = "gcc_gp1_clk",
1544 			.name = "gcc_gp2_clk",
1562 			.name = "gcc_gp3_clk",
1582 			.name = "gcc_gpu_cfg_ahb_clk",
1595 			.name = "gcc_gpu_gpll0_clk_src",
1611 			.name = "gcc_gpu_gpll0_div_clk_src",
1628 			.name = "gcc_gpu_iref_clk",
1641 			.name = "gcc_gpu_memnoc_gfx_clk",
1654 			.name = "gcc_gpu_snoc_dvm_gfx_clk",
1667 			.name = "gcc_gpu_vs_clk",
1685 			.name = "gcc_mss_axis2_clk",
1700 			.name = "gcc_mss_cfg_ahb_clk",
1712 			.name = "gcc_mss_gpll0_div_clk_src",
1727 			.name = "gcc_mss_mfab_axis_clk",
1740 			.name = "gcc_mss_q6_memnoc_axi_clk",
1753 			.name = "gcc_mss_snoc_axi_clk",
1766 			.name = "gcc_mss_vs_clk",
1784 			.name = "gcc_pcie_0_aux_clk",
1804 			.name = "gcc_pcie_0_cfg_ahb_clk",
1817 			.name = "gcc_pcie_0_clkref_clk",
1830 			.name = "gcc_pcie_0_mstr_axi_clk",
1842 			.name = "gcc_pcie_0_pipe_clk",
1844 				.fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk",
1862 			.name = "gcc_pcie_0_slv_axi_clk",
1875 			.name = "gcc_pcie_0_slv_q2a_axi_clk",
1888 			.name = "gcc_pcie_1_aux_clk",
1908 			.name = "gcc_pcie_1_cfg_ahb_clk",
1921 			.name = "gcc_pcie_1_clkref_clk",
1934 			.name = "gcc_pcie_1_mstr_axi_clk",
1946 			.name = "gcc_pcie_1_pipe_clk",
1948 				.fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk",
1965 			.name = "gcc_pcie_1_slv_axi_clk",
1978 			.name = "gcc_pcie_1_slv_q2a_axi_clk",
1991 			.name = "gcc_pcie_phy_aux_clk",
2009 			.name = "gcc_pcie_phy_refgen_clk",
2027 			.name = "gcc_pdm2_clk",
2047 			.name = "gcc_pdm_ahb_clk",
2060 			.name = "gcc_pdm_xo4_clk",
2075 			.name = "gcc_prng_ahb_clk",
2090 			.name = "gcc_qmip_camera_ahb_clk",
2105 			.name = "gcc_qmip_disp_ahb_clk",
2120 			.name = "gcc_qmip_video_ahb_clk",
2133 			.name = "gcc_qspi_cnoc_periph_ahb_clk",
2146 			.name = "gcc_qspi_core_clk",
2164 			.name = "gcc_qupv3_wrap0_s0_clk",
2182 			.name = "gcc_qupv3_wrap0_s1_clk",
2200 			.name = "gcc_qupv3_wrap0_s2_clk",
2218 			.name = "gcc_qupv3_wrap0_s3_clk",
2236 			.name = "gcc_qupv3_wrap0_s4_clk",
2254 			.name = "gcc_qupv3_wrap0_s5_clk",
2272 			.name = "gcc_qupv3_wrap0_s6_clk",
2290 			.name = "gcc_qupv3_wrap0_s7_clk",
2308 			.name = "gcc_qupv3_wrap1_s0_clk",
2326 			.name = "gcc_qupv3_wrap1_s1_clk",
2344 			.name = "gcc_qupv3_wrap1_s2_clk",
2362 			.name = "gcc_qupv3_wrap1_s3_clk",
2380 			.name = "gcc_qupv3_wrap1_s4_clk",
2398 			.name = "gcc_qupv3_wrap1_s5_clk",
2416 			.name = "gcc_qupv3_wrap1_s6_clk",
2434 			.name = "gcc_qupv3_wrap1_s7_clk",
2452 			.name = "gcc_qupv3_wrap_0_m_ahb_clk",
2467 			.name = "gcc_qupv3_wrap_0_s_ahb_clk",
2480 			.name = "gcc_qupv3_wrap_1_m_ahb_clk",
2495 			.name = "gcc_qupv3_wrap_1_s_ahb_clk",
2508 			.name = "gcc_sdcc1_ahb_clk",
2521 			.name = "gcc_sdcc1_apps_clk",
2539 			.name = "gcc_sdcc1_ice_core_clk",
2557 			.name = "gcc_sdcc2_ahb_clk",
2570 			.name = "gcc_sdcc2_apps_clk",
2588 			.name = "gcc_sdcc4_ahb_clk",
2601 			.name = "gcc_sdcc4_apps_clk",
2623 			.name = "gcc_sdcc4_apps_clk",
2641 			.name = "gcc_sys_noc_cpuss_ahb_clk",
2659 			.name = "gcc_tsif_ahb_clk",
2672 			.name = "gcc_tsif_inactivity_timers_clk",
2685 			.name = "gcc_tsif_ref_clk",
2705 			.name = "gcc_ufs_card_ahb_clk",
2720 			.name = "gcc_ufs_card_axi_clk",
2738 			.name = "gcc_ufs_card_clkref_clk",
2753 			.name = "gcc_ufs_card_ice_core_clk",
2773 			.name = "gcc_ufs_card_phy_aux_clk",
2790 			.name = "gcc_ufs_card_rx_symbol_0_clk",
2802 			.name = "gcc_ufs_card_rx_symbol_1_clk",
2814 			.name = "gcc_ufs_card_tx_symbol_0_clk",
2829 			.name = "gcc_ufs_card_unipro_core_clk",
2847 			.name = "gcc_ufs_mem_clkref_clk",
2862 			.name = "gcc_ufs_phy_ahb_clk",
2877 			.name = "gcc_ufs_phy_axi_clk",
2897 			.name = "gcc_ufs_phy_ice_core_clk",
2917 			.name = "gcc_ufs_phy_phy_aux_clk",
2934 			.name = "gcc_ufs_phy_rx_symbol_0_clk",
2946 			.name = "gcc_ufs_phy_rx_symbol_1_clk",
2958 			.name = "gcc_ufs_phy_tx_symbol_0_clk",
2973 			.name = "gcc_ufs_phy_unipro_core_clk",
2991 			.name = "gcc_usb30_prim_master_clk",
3009 			.name = "gcc_usb30_prim_mock_utmi_clk",
3027 			.name = "gcc_usb30_prim_sleep_clk",
3040 			.name = "gcc_usb30_sec_master_clk",
3058 			.name = "gcc_usb30_sec_mock_utmi_clk",
3076 			.name = "gcc_usb30_sec_sleep_clk",
3089 			.name = "gcc_usb3_prim_clkref_clk",
3102 			.name = "gcc_usb3_prim_phy_aux_clk",
3120 			.name = "gcc_usb3_prim_phy_com_aux_clk",
3137 			.name = "gcc_usb3_prim_phy_pipe_clk",
3150 			.name = "gcc_usb3_sec_clkref_clk",
3163 			.name = "gcc_usb3_sec_phy_aux_clk",
3181 			.name = "gcc_usb3_sec_phy_com_aux_clk",
3198 			.name = "gcc_usb3_sec_phy_pipe_clk",
3213 			.name = "gcc_usb_phy_cfg_ahb2phy_clk",
3226 			.name = "gcc_vdda_vs_clk",
3244 			.name = "gcc_vddcx_vs_clk",
3262 			.name = "gcc_vddmx_vs_clk",
3282 			.name = "gcc_video_ahb_clk",
3296 			.name = "gcc_video_axi_clk",
3309 			.name = "gcc_video_xo_clk",
3325 			.name = "gcc_vs_ctrl_ahb_clk",
3338 			.name = "gcc_vs_ctrl_clk",
3356 			.name = "gcc_cpuss_dvm_bus_clk",
3372 			.name = "gcc_cpuss_gnoc_clk",
3388 			.name = "gcc_lpass_q6_axi_clk",
3402 			.name = "gcc_lpass_sway_clk",
3413 		.name = "pcie_0_gdsc",
3422 		.name = "pcie_1_gdsc",
3431 		.name = "ufs_card_gdsc",
3440 		.name = "ufs_phy_gdsc",
3449 		.name = "usb30_prim_gdsc",
3458 		.name = "usb30_sec_gdsc",
3467 		.name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
3476 		.name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
3485 		.name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
3494 		.name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
3503 		.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3512 		.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3521 		.name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
4020 		.name	= "gcc-sdm845",