Lines Matching +full:0 +full:x33000
43 { 249600000, 2000000000, 0 },
47 .offset = 0x0,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
66 { 0x0, 1 },
67 { 0x1, 2 },
68 { 0x3, 4 },
69 { 0x7, 8 },
74 .offset = 0x0,
89 .offset = 0x1000,
94 .enable_reg = 0x52000,
108 .offset = 0x76000,
113 .enable_reg = 0x52000,
127 .offset = 0x1a000,
132 .enable_reg = 0x52000,
146 .offset = 0x1c000,
149 .enable_reg = 0x52000,
163 { P_BI_TCXO, 0 },
175 { P_BI_TCXO, 0 },
189 { P_BI_TCXO, 0 },
199 { P_BI_TCXO, 0 },
219 { P_BI_TCXO, 0 },
227 { P_BI_TCXO, 0 },
237 { P_BI_TCXO, 0 },
251 { P_BI_TCXO, 0 },
267 { P_BI_TCXO, 0 },
281 F(19200000, P_BI_TCXO, 1, 0, 0),
282 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
283 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
284 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
289 .cmd_rcgr = 0x6038,
290 .mnd_width = 0,
306 F(19200000, P_BI_TCXO, 1, 0, 0),
307 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
308 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
309 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
310 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
315 .cmd_rcgr = 0x601c,
330 F(19200000, P_BI_TCXO, 1, 0, 0),
331 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
332 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
333 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
334 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
339 .cmd_rcgr = 0x64004,
354 .cmd_rcgr = 0x65004,
369 .cmd_rcgr = 0x66004,
384 .cmd_rcgr = 0xbe004,
399 .cmd_rcgr = 0xbf004,
414 F(19200000, P_BI_TCXO, 1, 0, 0),
415 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
416 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
417 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
418 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
419 F(403000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
420 F(533000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
425 .cmd_rcgr = 0x4d014,
426 .mnd_width = 0,
440 F(9600000, P_BI_TCXO, 2, 0, 0),
441 F(19200000, P_BI_TCXO, 1, 0, 0),
446 .cmd_rcgr = 0x6b02c,
461 .cmd_rcgr = 0x8d02c,
476 .cmd_rcgr = 0x9d02c,
491 .cmd_rcgr = 0xa302c,
506 F(19200000, P_BI_TCXO, 1, 0, 0),
507 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
512 .cmd_rcgr = 0x6f014,
513 .mnd_width = 0,
527 F(9600000, P_BI_TCXO, 2, 0, 0),
528 F(19200000, P_BI_TCXO, 1, 0, 0),
529 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
534 .cmd_rcgr = 0x33010,
535 .mnd_width = 0,
549 F(19200000, P_BI_TCXO, 1, 0, 0),
550 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
551 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
552 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
557 .cmd_rcgr = 0x4a00c,
558 .mnd_width = 0,
572 .cmd_rcgr = 0x4b008,
573 .mnd_width = 0,
589 F(19200000, P_BI_TCXO, 1, 0, 0),
593 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
595 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
598 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
602 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
608 .cmd_rcgr = 0x17148,
623 .cmd_rcgr = 0x17278,
638 .cmd_rcgr = 0x173a8,
653 .cmd_rcgr = 0x174d8,
668 .cmd_rcgr = 0x17608,
683 .cmd_rcgr = 0x17738,
698 .cmd_rcgr = 0x17868,
713 .cmd_rcgr = 0x17998,
728 .cmd_rcgr = 0x18148,
743 .cmd_rcgr = 0x18278,
758 .cmd_rcgr = 0x183a8,
773 .cmd_rcgr = 0x184d8,
788 .cmd_rcgr = 0x18608,
803 .cmd_rcgr = 0x18738,
818 .cmd_rcgr = 0x1e148,
833 .cmd_rcgr = 0x1e278,
848 .cmd_rcgr = 0x1e3a8,
863 .cmd_rcgr = 0x1e4d8,
878 .cmd_rcgr = 0x1e608,
893 .cmd_rcgr = 0x1e738,
909 F(9600000, P_BI_TCXO, 2, 0, 0),
910 F(19200000, P_BI_TCXO, 1, 0, 0),
912 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
913 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
914 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
919 .cmd_rcgr = 0x1400c,
935 F(9600000, P_BI_TCXO, 2, 0, 0),
936 F(19200000, P_BI_TCXO, 1, 0, 0),
937 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
938 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
943 .cmd_rcgr = 0x1600c,
963 .cmd_rcgr = 0x36010,
978 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
979 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
980 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
981 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
986 .cmd_rcgr = 0xa2020,
1001 .cmd_rcgr = 0xa2060,
1002 .mnd_width = 0,
1016 F(19200000, P_BI_TCXO, 1, 0, 0),
1021 .cmd_rcgr = 0xa2094,
1022 .mnd_width = 0,
1036 .cmd_rcgr = 0xa2078,
1037 .mnd_width = 0,
1051 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1052 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1053 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1054 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1055 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1060 .cmd_rcgr = 0x75020,
1075 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1076 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1077 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1082 .cmd_rcgr = 0x75060,
1083 .mnd_width = 0,
1097 .cmd_rcgr = 0x75094,
1098 .mnd_width = 0,
1112 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1113 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1114 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1119 .cmd_rcgr = 0x75078,
1120 .mnd_width = 0,
1134 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1135 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1136 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1137 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1138 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1143 .cmd_rcgr = 0x77020,
1158 .cmd_rcgr = 0x77060,
1159 .mnd_width = 0,
1173 .cmd_rcgr = 0x77094,
1174 .mnd_width = 0,
1188 .cmd_rcgr = 0x77078,
1189 .mnd_width = 0,
1203 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1204 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1205 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1206 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1207 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1212 .cmd_rcgr = 0xa601c,
1227 F(19200000, P_BI_TCXO, 1, 0, 0),
1228 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1229 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1230 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1235 .cmd_rcgr = 0xa6034,
1236 .mnd_width = 0,
1250 .cmd_rcgr = 0xf01c,
1265 .cmd_rcgr = 0xf034,
1266 .mnd_width = 0,
1280 .cmd_rcgr = 0x1001c,
1295 .cmd_rcgr = 0x10034,
1296 .mnd_width = 0,
1310 .cmd_rcgr = 0xa6068,
1311 .mnd_width = 0,
1325 .cmd_rcgr = 0xf060,
1326 .mnd_width = 0,
1340 .cmd_rcgr = 0x10060,
1341 .mnd_width = 0,
1355 .halt_reg = 0x90018,
1358 .enable_reg = 0x90018,
1359 .enable_mask = BIT(0),
1368 .halt_reg = 0x750c0,
1370 .hwcg_reg = 0x750c0,
1373 .enable_reg = 0x750c0,
1374 .enable_mask = BIT(0),
1388 .halt_reg = 0x750c0,
1390 .hwcg_reg = 0x750c0,
1393 .enable_reg = 0x750c0,
1408 .halt_reg = 0x770c0,
1410 .hwcg_reg = 0x770c0,
1413 .enable_reg = 0x770c0,
1414 .enable_mask = BIT(0),
1428 .halt_reg = 0x770c0,
1430 .hwcg_reg = 0x770c0,
1433 .enable_reg = 0x770c0,
1448 .halt_reg = 0xa6084,
1451 .enable_reg = 0xa6084,
1452 .enable_mask = BIT(0),
1466 .halt_reg = 0xf07c,
1469 .enable_reg = 0xf07c,
1470 .enable_mask = BIT(0),
1484 .halt_reg = 0x1007c,
1487 .enable_reg = 0x1007c,
1488 .enable_mask = BIT(0),
1502 .halt_reg = 0x38004,
1504 .hwcg_reg = 0x38004,
1507 .enable_reg = 0x52004,
1517 .halt_reg = 0xb030,
1520 .enable_reg = 0xb030,
1521 .enable_mask = BIT(0),
1530 .halt_reg = 0xb034,
1533 .enable_reg = 0xb034,
1534 .enable_mask = BIT(0),
1543 .halt_reg = 0xa609c,
1546 .enable_reg = 0xa609c,
1547 .enable_mask = BIT(0),
1561 .halt_reg = 0xf078,
1564 .enable_reg = 0xf078,
1565 .enable_mask = BIT(0),
1579 .halt_reg = 0x10078,
1582 .enable_reg = 0x10078,
1583 .enable_mask = BIT(0),
1597 .halt_reg = 0x48008,
1600 .enable_reg = 0x48008,
1601 .enable_mask = BIT(0),
1610 .halt_reg = 0x71154,
1613 .enable_reg = 0x71154,
1614 .enable_mask = BIT(0),
1623 .halt_reg = 0xb038,
1626 .enable_reg = 0xb038,
1627 .enable_mask = BIT(0),
1636 .halt_reg = 0xb03c,
1639 .enable_reg = 0xb03c,
1640 .enable_mask = BIT(0),
1649 .halt_reg = 0x6010,
1652 .enable_reg = 0x6010,
1653 .enable_mask = BIT(0),
1662 .halt_reg = 0x6034,
1665 .enable_reg = 0x6034,
1666 .enable_mask = BIT(0),
1680 .halt_reg = 0x6018,
1683 .enable_reg = 0x6018,
1684 .enable_mask = BIT(0),
1698 .halt_reg = 0x6014,
1700 .hwcg_reg = 0x6014,
1703 .enable_reg = 0x6014,
1704 .enable_mask = BIT(0),
1713 .halt_reg = 0x64000,
1716 .enable_reg = 0x64000,
1717 .enable_mask = BIT(0),
1731 .halt_reg = 0x65000,
1734 .enable_reg = 0x65000,
1735 .enable_mask = BIT(0),
1749 .halt_reg = 0x66000,
1752 .enable_reg = 0x66000,
1753 .enable_mask = BIT(0),
1767 .halt_reg = 0xbe000,
1770 .enable_reg = 0xbe000,
1771 .enable_mask = BIT(0),
1785 .halt_reg = 0xbf000,
1788 .enable_reg = 0xbf000,
1789 .enable_mask = BIT(0),
1805 .enable_reg = 0x52004,
1820 .enable_reg = 0x52004,
1835 .halt_reg = 0x7100c,
1838 .enable_reg = 0x7100c,
1839 .enable_mask = BIT(0),
1848 .halt_reg = 0x71018,
1851 .enable_reg = 0x71018,
1852 .enable_mask = BIT(0),
1861 .halt_reg = 0x4d010,
1864 .enable_reg = 0x4d010,
1865 .enable_mask = BIT(0),
1874 .halt_reg = 0x4d008,
1877 .enable_reg = 0x4d008,
1878 .enable_mask = BIT(0),
1894 .enable_reg = 0x52004,
1909 .enable_reg = 0x52004,
1924 .halt_reg = 0x4d00c,
1927 .enable_reg = 0x4d00c,
1928 .enable_mask = BIT(0),
1937 .halt_reg = 0x6f02c,
1940 .enable_reg = 0x6f02c,
1941 .enable_mask = BIT(0),
1955 .halt_reg = 0x6f030,
1958 .enable_reg = 0x6f030,
1959 .enable_mask = BIT(0),
1973 .halt_reg = 0x6f034,
1976 .enable_reg = 0x6f034,
1977 .enable_mask = BIT(0),
1991 .halt_reg = 0x6f038,
1994 .enable_reg = 0x6f038,
1995 .enable_mask = BIT(0),
2009 .halt_reg = 0x6b020,
2012 .enable_reg = 0x5200c,
2027 .halt_reg = 0x6b01c,
2029 .hwcg_reg = 0x6b01c,
2032 .enable_reg = 0x5200c,
2042 .halt_reg = 0x8c00c,
2045 .enable_reg = 0x8c00c,
2046 .enable_mask = BIT(0),
2055 .halt_reg = 0x6b018,
2058 .enable_reg = 0x5200c,
2068 .halt_reg = 0x6b024,
2071 .enable_reg = 0x5200c,
2081 .halt_reg = 0x6b014,
2083 .hwcg_reg = 0x6b014,
2086 .enable_reg = 0x5200c,
2087 .enable_mask = BIT(0),
2096 .halt_reg = 0x6b010,
2099 .enable_reg = 0x5200c,
2109 .halt_reg = 0x8d020,
2112 .enable_reg = 0x52004,
2127 .halt_reg = 0x8d01c,
2129 .hwcg_reg = 0x8d01c,
2132 .enable_reg = 0x52004,
2142 .halt_reg = 0x8c02c,
2145 .enable_reg = 0x8c02c,
2146 .enable_mask = BIT(0),
2155 .halt_reg = 0x8d018,
2158 .enable_reg = 0x52004,
2168 .halt_reg = 0x8d024,
2171 .enable_reg = 0x52004,
2181 .halt_reg = 0x8d014,
2183 .hwcg_reg = 0x8d014,
2186 .enable_reg = 0x52004,
2196 .halt_reg = 0x8d010,
2199 .enable_reg = 0x52004,
2209 .halt_reg = 0x9d020,
2212 .enable_reg = 0x52014,
2227 .halt_reg = 0x9d01c,
2229 .hwcg_reg = 0x9d01c,
2232 .enable_reg = 0x52014,
2242 .halt_reg = 0x8c014,
2245 .enable_reg = 0x8c014,
2246 .enable_mask = BIT(0),
2255 .halt_reg = 0x9d018,
2258 .enable_reg = 0x52014,
2268 .halt_reg = 0x9d024,
2271 .enable_reg = 0x52014,
2281 .halt_reg = 0x9d014,
2283 .hwcg_reg = 0x9d014,
2286 .enable_reg = 0x52014,
2296 .halt_reg = 0x9d010,
2299 .enable_reg = 0x52014,
2309 .halt_reg = 0xa3020,
2312 .enable_reg = 0x52014,
2327 .halt_reg = 0xa301c,
2329 .hwcg_reg = 0xa301c,
2332 .enable_reg = 0x52014,
2342 .halt_reg = 0x8c018,
2345 .enable_reg = 0x8c018,
2346 .enable_mask = BIT(0),
2355 .halt_reg = 0xa3018,
2358 .enable_reg = 0x52014,
2368 .halt_reg = 0xa3024,
2371 .enable_reg = 0x52014,
2381 .halt_reg = 0xa3014,
2383 .hwcg_reg = 0xa3014,
2386 .enable_reg = 0x52014,
2396 .halt_reg = 0xa3010,
2399 .enable_reg = 0x52014,
2409 .halt_reg = 0x6f004,
2412 .enable_reg = 0x6f004,
2413 .enable_mask = BIT(0),
2427 .halt_reg = 0x3300c,
2430 .enable_reg = 0x3300c,
2431 .enable_mask = BIT(0),
2445 .halt_reg = 0x33004,
2447 .hwcg_reg = 0x33004,
2450 .enable_reg = 0x33004,
2451 .enable_mask = BIT(0),
2460 .halt_reg = 0x33008,
2463 .enable_reg = 0x33008,
2464 .enable_mask = BIT(0),
2473 .halt_reg = 0x34004,
2476 .enable_reg = 0x52004,
2486 .halt_reg = 0xb018,
2488 .hwcg_reg = 0xb018,
2491 .enable_reg = 0xb018,
2492 .enable_mask = BIT(0),
2501 .halt_reg = 0xb01c,
2503 .hwcg_reg = 0xb01c,
2506 .enable_reg = 0xb01c,
2507 .enable_mask = BIT(0),
2516 .halt_reg = 0xb020,
2518 .hwcg_reg = 0xb020,
2521 .enable_reg = 0xb020,
2522 .enable_mask = BIT(0),
2531 .halt_reg = 0xb010,
2533 .hwcg_reg = 0xb010,
2536 .enable_reg = 0xb010,
2537 .enable_mask = BIT(0),
2546 .halt_reg = 0xb014,
2548 .hwcg_reg = 0xb014,
2551 .enable_reg = 0xb014,
2552 .enable_mask = BIT(0),
2561 .halt_reg = 0x4a004,
2564 .enable_reg = 0x4a004,
2565 .enable_mask = BIT(0),
2574 .halt_reg = 0x4a008,
2577 .enable_reg = 0x4a008,
2578 .enable_mask = BIT(0),
2592 .halt_reg = 0x4b000,
2595 .enable_reg = 0x4b000,
2596 .enable_mask = BIT(0),
2605 .halt_reg = 0x4b004,
2608 .enable_reg = 0x4b004,
2609 .enable_mask = BIT(0),
2623 .halt_reg = 0x17144,
2626 .enable_reg = 0x5200c,
2641 .halt_reg = 0x17274,
2644 .enable_reg = 0x5200c,
2659 .halt_reg = 0x173a4,
2662 .enable_reg = 0x5200c,
2677 .halt_reg = 0x174d4,
2680 .enable_reg = 0x5200c,
2695 .halt_reg = 0x17604,
2698 .enable_reg = 0x5200c,
2713 .halt_reg = 0x17734,
2716 .enable_reg = 0x5200c,
2731 .halt_reg = 0x17864,
2734 .enable_reg = 0x5200c,
2749 .halt_reg = 0x17994,
2752 .enable_reg = 0x5200c,
2767 .halt_reg = 0x18144,
2770 .enable_reg = 0x5200c,
2785 .halt_reg = 0x18274,
2788 .enable_reg = 0x5200c,
2803 .halt_reg = 0x183a4,
2806 .enable_reg = 0x5200c,
2821 .halt_reg = 0x184d4,
2824 .enable_reg = 0x5200c,
2839 .halt_reg = 0x18604,
2842 .enable_reg = 0x5200c,
2857 .halt_reg = 0x18734,
2860 .enable_reg = 0x5200c,
2875 .halt_reg = 0x1e144,
2878 .enable_reg = 0x52014,
2893 .halt_reg = 0x1e274,
2896 .enable_reg = 0x52014,
2911 .halt_reg = 0x1e3a4,
2914 .enable_reg = 0x52014,
2929 .halt_reg = 0x1e4d4,
2932 .enable_reg = 0x52014,
2947 .halt_reg = 0x1e604,
2950 .enable_reg = 0x52014,
2965 .halt_reg = 0x1e734,
2968 .enable_reg = 0x52014,
2983 .halt_reg = 0x17004,
2986 .enable_reg = 0x5200c,
2996 .halt_reg = 0x17008,
2998 .hwcg_reg = 0x17008,
3001 .enable_reg = 0x5200c,
3011 .halt_reg = 0x18004,
3014 .enable_reg = 0x5200c,
3024 .halt_reg = 0x18008,
3026 .hwcg_reg = 0x18008,
3029 .enable_reg = 0x5200c,
3039 .halt_reg = 0x1e004,
3042 .enable_reg = 0x52014,
3052 .halt_reg = 0x1e008,
3054 .hwcg_reg = 0x1e008,
3057 .enable_reg = 0x52014,
3067 .halt_reg = 0x14008,
3070 .enable_reg = 0x14008,
3071 .enable_mask = BIT(0),
3080 .halt_reg = 0x14004,
3083 .enable_reg = 0x14004,
3084 .enable_mask = BIT(0),
3098 .halt_reg = 0x16008,
3101 .enable_reg = 0x16008,
3102 .enable_mask = BIT(0),
3111 .halt_reg = 0x16004,
3114 .enable_reg = 0x16004,
3115 .enable_mask = BIT(0),
3129 .halt_reg = 0x36004,
3132 .enable_reg = 0x36004,
3133 .enable_mask = BIT(0),
3142 .halt_reg = 0x3600c,
3145 .enable_reg = 0x3600c,
3146 .enable_mask = BIT(0),
3155 .halt_reg = 0x36008,
3158 .enable_reg = 0x36008,
3159 .enable_mask = BIT(0),
3173 .halt_reg = 0xa2014,
3175 .hwcg_reg = 0xa2014,
3178 .enable_reg = 0xa2014,
3179 .enable_mask = BIT(0),
3188 .halt_reg = 0xa2010,
3190 .hwcg_reg = 0xa2010,
3193 .enable_reg = 0xa2010,
3194 .enable_mask = BIT(0),
3208 .halt_reg = 0xa205c,
3210 .hwcg_reg = 0xa205c,
3213 .enable_reg = 0xa205c,
3214 .enable_mask = BIT(0),
3228 .halt_reg = 0xa2090,
3230 .hwcg_reg = 0xa2090,
3233 .enable_reg = 0xa2090,
3234 .enable_mask = BIT(0),
3248 .halt_reg = 0xa201c,
3251 .enable_reg = 0xa201c,
3252 .enable_mask = BIT(0),
3261 .halt_reg = 0xa20ac,
3264 .enable_reg = 0xa20ac,
3265 .enable_mask = BIT(0),
3274 .halt_reg = 0xa2018,
3277 .enable_reg = 0xa2018,
3278 .enable_mask = BIT(0),
3287 .halt_reg = 0xa2058,
3289 .hwcg_reg = 0xa2058,
3292 .enable_reg = 0xa2058,
3293 .enable_mask = BIT(0),
3307 .halt_reg = 0x75014,
3309 .hwcg_reg = 0x75014,
3312 .enable_reg = 0x75014,
3313 .enable_mask = BIT(0),
3322 .halt_reg = 0x75010,
3324 .hwcg_reg = 0x75010,
3327 .enable_reg = 0x75010,
3328 .enable_mask = BIT(0),
3342 .halt_reg = 0x75010,
3344 .hwcg_reg = 0x75010,
3347 .enable_reg = 0x75010,
3362 .halt_reg = 0x7505c,
3364 .hwcg_reg = 0x7505c,
3367 .enable_reg = 0x7505c,
3368 .enable_mask = BIT(0),
3382 .halt_reg = 0x7505c,
3384 .hwcg_reg = 0x7505c,
3387 .enable_reg = 0x7505c,
3402 .halt_reg = 0x75090,
3404 .hwcg_reg = 0x75090,
3407 .enable_reg = 0x75090,
3408 .enable_mask = BIT(0),
3422 .halt_reg = 0x75090,
3424 .hwcg_reg = 0x75090,
3427 .enable_reg = 0x75090,
3442 .halt_reg = 0x7501c,
3445 .enable_reg = 0x7501c,
3446 .enable_mask = BIT(0),
3455 .halt_reg = 0x750ac,
3458 .enable_reg = 0x750ac,
3459 .enable_mask = BIT(0),
3468 .halt_reg = 0x75018,
3471 .enable_reg = 0x75018,
3472 .enable_mask = BIT(0),
3481 .halt_reg = 0x75058,
3483 .hwcg_reg = 0x75058,
3486 .enable_reg = 0x75058,
3487 .enable_mask = BIT(0),
3501 .halt_reg = 0x75058,
3503 .hwcg_reg = 0x75058,
3506 .enable_reg = 0x75058,
3521 .halt_reg = 0x77014,
3523 .hwcg_reg = 0x77014,
3526 .enable_reg = 0x77014,
3527 .enable_mask = BIT(0),
3536 .halt_reg = 0x77010,
3538 .hwcg_reg = 0x77010,
3541 .enable_reg = 0x77010,
3542 .enable_mask = BIT(0),
3556 .halt_reg = 0x77010,
3558 .hwcg_reg = 0x77010,
3561 .enable_reg = 0x77010,
3576 .halt_reg = 0x7705c,
3578 .hwcg_reg = 0x7705c,
3581 .enable_reg = 0x7705c,
3582 .enable_mask = BIT(0),
3596 .halt_reg = 0x7705c,
3598 .hwcg_reg = 0x7705c,
3601 .enable_reg = 0x7705c,
3616 .halt_reg = 0x77090,
3618 .hwcg_reg = 0x77090,
3621 .enable_reg = 0x77090,
3622 .enable_mask = BIT(0),
3636 .halt_reg = 0x77090,
3638 .hwcg_reg = 0x77090,
3641 .enable_reg = 0x77090,
3656 .halt_reg = 0x7701c,
3659 .enable_reg = 0x7701c,
3660 .enable_mask = BIT(0),
3669 .halt_reg = 0x770ac,
3672 .enable_reg = 0x770ac,
3673 .enable_mask = BIT(0),
3682 .halt_reg = 0x77018,
3685 .enable_reg = 0x77018,
3686 .enable_mask = BIT(0),
3695 .halt_reg = 0x77058,
3697 .hwcg_reg = 0x77058,
3700 .enable_reg = 0x77058,
3701 .enable_mask = BIT(0),
3715 .halt_reg = 0x77058,
3717 .hwcg_reg = 0x77058,
3720 .enable_reg = 0x77058,
3735 .halt_reg = 0xa6010,
3738 .enable_reg = 0xa6010,
3739 .enable_mask = BIT(0),
3752 .halt_reg = 0xa6018,
3755 .enable_reg = 0xa6018,
3756 .enable_mask = BIT(0),
3770 .halt_reg = 0xa6014,
3773 .enable_reg = 0xa6014,
3774 .enable_mask = BIT(0),
3783 .halt_reg = 0xf010,
3786 .enable_reg = 0xf010,
3787 .enable_mask = BIT(0),
3800 .halt_reg = 0xf018,
3803 .enable_reg = 0xf018,
3804 .enable_mask = BIT(0),
3818 .halt_reg = 0xf014,
3821 .enable_reg = 0xf014,
3822 .enable_mask = BIT(0),
3831 .halt_reg = 0x10010,
3834 .enable_reg = 0x10010,
3835 .enable_mask = BIT(0),
3848 .halt_reg = 0x10018,
3851 .enable_reg = 0x10018,
3852 .enable_mask = BIT(0),
3866 .halt_reg = 0x10014,
3869 .enable_reg = 0x10014,
3870 .enable_mask = BIT(0),
3879 .halt_reg = 0xa6050,
3882 .enable_reg = 0xa6050,
3883 .enable_mask = BIT(0),
3897 .halt_reg = 0xa6054,
3900 .enable_reg = 0xa6054,
3901 .enable_mask = BIT(0),
3915 .halt_reg = 0xa6058,
3918 .enable_reg = 0xa6058,
3919 .enable_mask = BIT(0),
3928 .halt_reg = 0xa605c,
3931 .enable_reg = 0xa605c,
3932 .enable_mask = BIT(0),
3941 .halt_reg = 0x8c008,
3944 .enable_reg = 0x8c008,
3945 .enable_mask = BIT(0),
3954 .halt_reg = 0xf050,
3957 .enable_reg = 0xf050,
3958 .enable_mask = BIT(0),
3972 .halt_reg = 0xf054,
3975 .enable_reg = 0xf054,
3976 .enable_mask = BIT(0),
3990 .halt_reg = 0xf058,
3993 .enable_reg = 0xf058,
3994 .enable_mask = BIT(0),
4003 .halt_reg = 0x8c028,
4006 .enable_reg = 0x8c028,
4007 .enable_mask = BIT(0),
4016 .halt_reg = 0x10050,
4019 .enable_reg = 0x10050,
4020 .enable_mask = BIT(0),
4034 .halt_reg = 0x10054,
4037 .enable_reg = 0x10054,
4038 .enable_mask = BIT(0),
4052 .halt_reg = 0x10058,
4055 .enable_reg = 0x10058,
4056 .enable_mask = BIT(0),
4065 .halt_reg = 0xb024,
4068 .enable_reg = 0xb024,
4069 .enable_mask = BIT(0),
4078 .halt_reg = 0xb028,
4081 .enable_reg = 0xb028,
4082 .enable_mask = BIT(0),
4091 .halt_reg = 0xb02c,
4094 .enable_reg = 0xb02c,
4095 .enable_mask = BIT(0),
4104 .gdscr = 0x10004,
4113 .gdscr = 0x6004,
4122 .gdscr = 0xf004,
4131 .gdscr = 0x6b004,
4140 .gdscr = 0x75004,
4149 .gdscr = 0x77004,
4158 .gdscr = 0x8d004,
4167 .gdscr = 0x9d004,
4176 .gdscr = 0xa2004,
4185 .gdscr = 0xa3004,
4194 .gdscr = 0xa6004,
4443 [GCC_EMAC_BCR] = { 0x6000 },
4444 [GCC_GPU_BCR] = { 0x71000 },
4445 [GCC_MMSS_BCR] = { 0xb000 },
4446 [GCC_NPU_BCR] = { 0x4d000 },
4447 [GCC_PCIE_0_BCR] = { 0x6b000 },
4448 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
4449 [GCC_PCIE_1_BCR] = { 0x8d000 },
4450 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
4451 [GCC_PCIE_2_BCR] = { 0x9d000 },
4452 [GCC_PCIE_2_PHY_BCR] = { 0xa701c },
4453 [GCC_PCIE_3_BCR] = { 0xa3000 },
4454 [GCC_PCIE_3_PHY_BCR] = { 0xa801c },
4455 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
4456 [GCC_PDM_BCR] = { 0x33000 },
4457 [GCC_PRNG_BCR] = { 0x34000 },
4458 [GCC_QSPI_1_BCR] = { 0x4a000 },
4459 [GCC_QSPI_BCR] = { 0x24008 },
4460 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
4461 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
4462 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
4463 [GCC_QUSB2PHY_5_BCR] = { 0x12010 },
4464 [GCC_QUSB2PHY_MP0_BCR] = { 0x12008 },
4465 [GCC_QUSB2PHY_MP1_BCR] = { 0x1200c },
4466 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
4467 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
4468 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 },
4469 [GCC_USB3_PHY_PRIM_SP1_BCR] = { 0x50004 },
4470 [GCC_USB3_DP_PHY_PRIM_SP0_BCR] = { 0x50010 },
4471 [GCC_USB3_DP_PHY_PRIM_SP1_BCR] = { 0x50014 },
4472 [GCC_USB3_PHY_SEC_BCR] = { 0x50018 },
4473 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
4474 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
4475 [GCC_SDCC2_BCR] = { 0x14000 },
4476 [GCC_SDCC4_BCR] = { 0x16000 },
4477 [GCC_TSIF_BCR] = { 0x36000 },
4478 [GCC_UFS_CARD_2_BCR] = { 0xa2000 },
4479 [GCC_UFS_CARD_BCR] = { 0x75000 },
4480 [GCC_UFS_PHY_BCR] = { 0x77000 },
4481 [GCC_USB30_MP_BCR] = { 0xa6000 },
4482 [GCC_USB30_PRIM_BCR] = { 0xf000 },
4483 [GCC_USB30_SEC_BCR] = { 0x10000 },
4484 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
4485 [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },
4486 [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },
4487 [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },
4508 .max_register = 0xc0004,
4543 regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4544 regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4545 regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4546 regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4547 regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4548 regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4549 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4550 regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4551 regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4552 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4555 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sc8180x_probe()
4556 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sc8180x_probe()