Lines Matching +full:0 +full:x62000
76 .offset = 0x0,
79 .enable_reg = 0x4b028,
80 .enable_mask = BIT(0),
91 { 0x1, 2 },
96 .offset = 0x0,
113 .offset = 0x1000,
116 .enable_reg = 0x4b028,
128 .offset = 0x4000,
131 .enable_reg = 0x4b028,
143 .offset = 0x5000,
146 .enable_reg = 0x4b028,
158 .offset = 0x7000,
161 .enable_reg = 0x4b028,
173 .offset = 0x9000,
176 .enable_reg = 0x4b028,
188 { P_BI_TCXO, 0 },
200 { P_BI_TCXO, 0 },
214 { P_BI_TCXO, 0 },
228 { P_BI_TCXO, 0 },
238 { P_BI_TCXO, 0 },
254 { P_BI_TCXO, 0 },
262 { P_BI_TCXO, 0 },
276 { P_BI_TCXO, 0 },
290 { P_BI_TCXO, 0 },
324 { P_BI_TCXO, 0 },
340 { P_BI_TCXO, 0 },
350 { P_BI_TCXO, 0 },
366 { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
376 { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
386 { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
396 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
406 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
416 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
426 { P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 0 },
436 { P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, 0 },
446 .reg = 0xa9074,
447 .shift = 0,
461 .reg = 0xa906c,
475 .reg = 0x77074,
476 .shift = 0,
490 .reg = 0x7706c,
504 .reg = 0x81060,
505 .shift = 0,
519 .reg = 0x810d0,
520 .shift = 0,
534 .reg = 0x81050,
535 .shift = 0,
549 .reg = 0x83060,
550 .shift = 0,
564 .reg = 0x830d0,
565 .shift = 0,
579 .reg = 0x83050,
580 .shift = 0,
594 .reg = 0x1b068,
595 .shift = 0,
609 .reg = 0x2f068,
610 .shift = 0,
624 F(19200000, P_BI_TCXO, 1, 0, 0),
629 .cmd_rcgr = 0xb6028,
630 .mnd_width = 0,
643 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
644 F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0),
649 .cmd_rcgr = 0xb6060,
663 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
664 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
669 .cmd_rcgr = 0xb6048,
683 .cmd_rcgr = 0xb4028,
684 .mnd_width = 0,
697 .cmd_rcgr = 0xb4060,
711 .cmd_rcgr = 0xb4048,
725 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
726 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
731 .cmd_rcgr = 0x70004,
745 .cmd_rcgr = 0x71004,
759 .cmd_rcgr = 0x62004,
773 .cmd_rcgr = 0x1e004,
787 .cmd_rcgr = 0x1f004,
801 .cmd_rcgr = 0xa9078,
815 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
820 .cmd_rcgr = 0xa9054,
821 .mnd_width = 0,
834 .cmd_rcgr = 0x77078,
848 .cmd_rcgr = 0x77054,
849 .mnd_width = 0,
862 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
867 .cmd_rcgr = 0x3f010,
868 .mnd_width = 0,
883 F(19200000, P_BI_TCXO, 1, 0, 0),
890 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
902 .cmd_rcgr = 0x23154,
918 .cmd_rcgr = 0x23288,
929 F(19200000, P_BI_TCXO, 1, 0, 0),
936 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
948 .cmd_rcgr = 0x233bc,
964 .cmd_rcgr = 0x234f0,
980 .cmd_rcgr = 0x23624,
996 .cmd_rcgr = 0x23758,
1012 .cmd_rcgr = 0x2388c,
1028 .cmd_rcgr = 0x24154,
1044 .cmd_rcgr = 0x24288,
1060 .cmd_rcgr = 0x243bc,
1076 .cmd_rcgr = 0x244f0,
1092 .cmd_rcgr = 0x24624,
1108 .cmd_rcgr = 0x24758,
1124 .cmd_rcgr = 0x2488c,
1140 .cmd_rcgr = 0x2a154,
1156 .cmd_rcgr = 0x2a288,
1172 .cmd_rcgr = 0x2a3bc,
1188 .cmd_rcgr = 0x2a4f0,
1204 .cmd_rcgr = 0x2a624,
1220 .cmd_rcgr = 0x2a758,
1236 .cmd_rcgr = 0x2a88c,
1247 F(19200000, P_BI_TCXO, 1, 0, 0),
1252 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1255 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1256 F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1268 .cmd_rcgr = 0xc4154,
1279 F(19200000, P_BI_TCXO, 1, 0, 0),
1281 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1282 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1283 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1284 F(192000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1285 F(384000000, P_GCC_GPLL9_OUT_MAIN, 2, 0, 0),
1290 .cmd_rcgr = 0x20014,
1304 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1305 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1310 .cmd_rcgr = 0x2002c,
1311 .mnd_width = 0,
1329 .cmd_rcgr = 0x21008,
1343 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1344 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1345 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1346 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1347 F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1352 .cmd_rcgr = 0x8102c,
1366 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1367 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1368 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1369 F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1374 .cmd_rcgr = 0x81074,
1375 .mnd_width = 0,
1388 .cmd_rcgr = 0x810a8,
1389 .mnd_width = 0,
1402 .cmd_rcgr = 0x8108c,
1403 .mnd_width = 0,
1416 .cmd_rcgr = 0x8302c,
1430 .cmd_rcgr = 0x83074,
1431 .mnd_width = 0,
1444 .cmd_rcgr = 0x830a8,
1445 .mnd_width = 0,
1458 .cmd_rcgr = 0x8308c,
1459 .mnd_width = 0,
1472 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1477 .cmd_rcgr = 0x1c028,
1491 .cmd_rcgr = 0x1c040,
1492 .mnd_width = 0,
1505 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1506 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1507 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1512 .cmd_rcgr = 0x1b028,
1526 .cmd_rcgr = 0x1b040,
1527 .mnd_width = 0,
1540 .cmd_rcgr = 0x2f028,
1554 .cmd_rcgr = 0x2f040,
1555 .mnd_width = 0,
1568 .cmd_rcgr = 0x1b06c,
1569 .mnd_width = 0,
1582 .cmd_rcgr = 0x2f06c,
1583 .mnd_width = 0,
1596 .reg = 0xa9070,
1597 .shift = 0,
1611 .reg = 0x77070,
1612 .shift = 0,
1626 .reg = 0xc4284,
1627 .shift = 0,
1641 .reg = 0x1c058,
1642 .shift = 0,
1656 .reg = 0x1b058,
1657 .shift = 0,
1671 .reg = 0x2f058,
1672 .shift = 0,
1686 .halt_reg = 0x8e200,
1688 .hwcg_reg = 0x8e200,
1691 .enable_reg = 0x4b000,
1701 .halt_reg = 0x810d4,
1703 .hwcg_reg = 0x810d4,
1706 .enable_reg = 0x810d4,
1707 .enable_mask = BIT(0),
1721 .halt_reg = 0x830d4,
1723 .hwcg_reg = 0x830d4,
1726 .enable_reg = 0x830d4,
1727 .enable_mask = BIT(0),
1741 .halt_reg = 0x830d4,
1743 .hwcg_reg = 0x830d4,
1746 .enable_reg = 0x830d4,
1761 .halt_reg = 0x1c05c,
1763 .hwcg_reg = 0x1c05c,
1766 .enable_reg = 0x1c05c,
1767 .enable_mask = BIT(0),
1781 .halt_reg = 0x1b084,
1783 .hwcg_reg = 0x1b084,
1786 .enable_reg = 0x1b084,
1787 .enable_mask = BIT(0),
1801 .halt_reg = 0x2f088,
1803 .hwcg_reg = 0x2f088,
1806 .enable_reg = 0x2f088,
1807 .enable_mask = BIT(0),
1821 .halt_reg = 0x76004,
1823 .hwcg_reg = 0x76004,
1826 .enable_reg = 0x76004,
1827 .enable_mask = BIT(0),
1836 .halt_reg = 0x76008,
1838 .hwcg_reg = 0x76008,
1841 .enable_reg = 0x76008,
1842 .enable_mask = BIT(0),
1851 .halt_reg = 0x7600c,
1853 .hwcg_reg = 0x7600c,
1856 .enable_reg = 0x7600c,
1857 .enable_mask = BIT(0),
1866 .halt_reg = 0x44004,
1868 .hwcg_reg = 0x44004,
1871 .enable_reg = 0x4b000,
1881 .halt_reg = 0x32010,
1883 .hwcg_reg = 0x32010,
1886 .enable_reg = 0x32010,
1887 .enable_mask = BIT(0),
1896 .halt_reg = 0x32018,
1898 .hwcg_reg = 0x32018,
1901 .enable_reg = 0x32018,
1902 .enable_mask = BIT(0),
1911 .halt_reg = 0x32024,
1914 .enable_reg = 0x32024,
1915 .enable_mask = BIT(0),
1924 .halt_reg = 0x1c060,
1926 .hwcg_reg = 0x1c060,
1929 .enable_reg = 0x1c060,
1930 .enable_mask = BIT(0),
1944 .halt_reg = 0x1b088,
1946 .hwcg_reg = 0x1b088,
1949 .enable_reg = 0x1b088,
1950 .enable_mask = BIT(0),
1964 .halt_reg = 0x2f084,
1966 .hwcg_reg = 0x2f084,
1969 .enable_reg = 0x2f084,
1970 .enable_mask = BIT(0),
1984 .halt_reg = 0x7d164,
1986 .hwcg_reg = 0x7d164,
1989 .enable_reg = 0x7d164,
1990 .enable_mask = BIT(0),
1999 .halt_reg = 0xc7010,
2001 .hwcg_reg = 0xc7010,
2004 .enable_reg = 0xc7010,
2005 .enable_mask = BIT(0),
2014 .halt_reg = 0x33010,
2016 .hwcg_reg = 0x33010,
2019 .enable_reg = 0x33010,
2020 .enable_mask = BIT(0),
2029 .halt_reg = 0x97448,
2032 .enable_reg = 0x97448,
2033 .enable_mask = BIT(0),
2042 .halt_reg = 0xb6018,
2044 .hwcg_reg = 0xb6018,
2047 .enable_reg = 0xb6018,
2048 .enable_mask = BIT(0),
2057 .halt_reg = 0xb6024,
2060 .enable_reg = 0xb6024,
2061 .enable_mask = BIT(0),
2075 .halt_reg = 0xb6040,
2078 .enable_reg = 0xb6040,
2079 .enable_mask = BIT(0),
2093 .halt_reg = 0xb6044,
2096 .enable_reg = 0xb6044,
2097 .enable_mask = BIT(0),
2111 .halt_reg = 0xb6020,
2113 .hwcg_reg = 0xb6020,
2116 .enable_reg = 0xb6020,
2117 .enable_mask = BIT(0),
2126 .halt_reg = 0xb4018,
2128 .hwcg_reg = 0xb4018,
2131 .enable_reg = 0xb4018,
2132 .enable_mask = BIT(0),
2141 .halt_reg = 0xb4024,
2144 .enable_reg = 0xb4024,
2145 .enable_mask = BIT(0),
2159 .halt_reg = 0xb4040,
2162 .enable_reg = 0xb4040,
2163 .enable_mask = BIT(0),
2177 .halt_reg = 0xb4044,
2180 .enable_reg = 0xb4044,
2181 .enable_mask = BIT(0),
2195 .halt_reg = 0xb4020,
2197 .hwcg_reg = 0xb4020,
2200 .enable_reg = 0xb4020,
2201 .enable_mask = BIT(0),
2210 .halt_reg = 0x70000,
2213 .enable_reg = 0x70000,
2214 .enable_mask = BIT(0),
2228 .halt_reg = 0x71000,
2231 .enable_reg = 0x71000,
2232 .enable_mask = BIT(0),
2246 .halt_reg = 0x62000,
2249 .enable_reg = 0x62000,
2250 .enable_mask = BIT(0),
2264 .halt_reg = 0x1e000,
2267 .enable_reg = 0x1e000,
2268 .enable_mask = BIT(0),
2282 .halt_reg = 0x1f000,
2285 .enable_reg = 0x1f000,
2286 .enable_mask = BIT(0),
2302 .enable_reg = 0x4b000,
2319 .enable_reg = 0x4b000,
2334 .halt_reg = 0x7d010,
2336 .hwcg_reg = 0x7d010,
2339 .enable_reg = 0x7d010,
2340 .enable_mask = BIT(0),
2349 .halt_reg = 0x7d01c,
2352 .enable_reg = 0x7d01c,
2353 .enable_mask = BIT(0),
2362 .halt_reg = 0x7d008,
2364 .hwcg_reg = 0x7d008,
2367 .enable_reg = 0x7d008,
2368 .enable_mask = BIT(0),
2377 .halt_reg = 0x7d014,
2379 .hwcg_reg = 0x7d014,
2382 .enable_reg = 0x7d014,
2383 .enable_mask = BIT(0),
2392 .halt_reg = 0xa9038,
2395 .enable_reg = 0x4b010,
2410 .halt_reg = 0xa902c,
2412 .hwcg_reg = 0xa902c,
2415 .enable_reg = 0x4b010,
2425 .halt_reg = 0xa9024,
2428 .enable_reg = 0x4b010,
2438 .halt_reg = 0xa9030,
2441 .enable_reg = 0x4b010,
2456 .halt_reg = 0xa9050,
2459 .enable_reg = 0x4b010,
2474 .halt_reg = 0xa9040,
2477 .enable_reg = 0x4b010,
2492 .halt_reg = 0xa9048,
2495 .enable_reg = 0x4b018,
2510 .halt_reg = 0xa901c,
2513 .enable_reg = 0x4b010,
2523 .halt_reg = 0xa9018,
2526 .enable_reg = 0x4b018,
2536 .halt_reg = 0x77038,
2539 .enable_reg = 0x4b000,
2554 .halt_reg = 0x7702c,
2556 .hwcg_reg = 0x7702c,
2559 .enable_reg = 0x4b008,
2569 .halt_reg = 0x77024,
2572 .enable_reg = 0x4b008,
2582 .halt_reg = 0x77030,
2585 .enable_reg = 0x4b008,
2600 .halt_reg = 0x77050,
2603 .enable_reg = 0x4b000,
2618 .halt_reg = 0x77040,
2621 .enable_reg = 0x4b008,
2636 .halt_reg = 0x77048,
2639 .enable_reg = 0x4b018,
2654 .halt_reg = 0x7701c,
2657 .enable_reg = 0x4b008,
2658 .enable_mask = BIT(0),
2667 .halt_reg = 0x77018,
2670 .enable_reg = 0x4b008,
2680 .halt_reg = 0x9746c,
2683 .enable_reg = 0x9746c,
2684 .enable_mask = BIT(0),
2693 .halt_reg = 0xb2034,
2696 .enable_reg = 0x4b020,
2706 .halt_reg = 0x3f00c,
2709 .enable_reg = 0x3f00c,
2710 .enable_mask = BIT(0),
2724 .halt_reg = 0x3f004,
2726 .hwcg_reg = 0x3f004,
2729 .enable_reg = 0x3f004,
2730 .enable_mask = BIT(0),
2739 .halt_reg = 0x3f008,
2742 .enable_reg = 0x3f008,
2743 .enable_mask = BIT(0),
2752 .halt_reg = 0x32008,
2754 .hwcg_reg = 0x32008,
2757 .enable_reg = 0x32008,
2758 .enable_mask = BIT(0),
2767 .halt_reg = 0x3200c,
2769 .hwcg_reg = 0x3200c,
2772 .enable_reg = 0x3200c,
2773 .enable_mask = BIT(0),
2782 .halt_reg = 0xc7008,
2784 .hwcg_reg = 0xc7008,
2787 .enable_reg = 0xc7008,
2788 .enable_mask = BIT(0),
2797 .halt_reg = 0xc700c,
2800 .enable_reg = 0xc700c,
2801 .enable_mask = BIT(0),
2810 .halt_reg = 0x33008,
2812 .hwcg_reg = 0x33008,
2815 .enable_reg = 0x33008,
2816 .enable_mask = BIT(0),
2825 .halt_reg = 0x3300c,
2828 .enable_reg = 0x3300c,
2829 .enable_mask = BIT(0),
2838 .halt_reg = 0x34008,
2840 .hwcg_reg = 0x34008,
2843 .enable_reg = 0x34008,
2844 .enable_mask = BIT(0),
2853 .halt_reg = 0x3400c,
2855 .hwcg_reg = 0x3400c,
2858 .enable_reg = 0x3400c,
2859 .enable_mask = BIT(0),
2868 .halt_reg = 0x34010,
2870 .hwcg_reg = 0x34010,
2873 .enable_reg = 0x34010,
2874 .enable_mask = BIT(0),
2883 .halt_reg = 0x23018,
2886 .enable_reg = 0x4b008,
2896 .halt_reg = 0x2300c,
2899 .enable_reg = 0x4b008,
2909 .halt_reg = 0x2314c,
2912 .enable_reg = 0x4b008,
2927 .halt_reg = 0x23280,
2930 .enable_reg = 0x4b008,
2945 .halt_reg = 0x233b4,
2948 .enable_reg = 0x4b008,
2963 .halt_reg = 0x234e8,
2966 .enable_reg = 0x4b008,
2981 .halt_reg = 0x2361c,
2984 .enable_reg = 0x4b008,
2999 .halt_reg = 0x23750,
3002 .enable_reg = 0x4b008,
3017 .halt_reg = 0x23884,
3020 .enable_reg = 0x4b008,
3035 .halt_reg = 0x24018,
3038 .enable_reg = 0x4b008,
3048 .halt_reg = 0x2400c,
3051 .enable_reg = 0x4b008,
3061 .halt_reg = 0x2414c,
3064 .enable_reg = 0x4b008,
3079 .halt_reg = 0x24280,
3082 .enable_reg = 0x4b008,
3097 .halt_reg = 0x243b4,
3100 .enable_reg = 0x4b008,
3115 .halt_reg = 0x244e8,
3118 .enable_reg = 0x4b008,
3133 .halt_reg = 0x2461c,
3136 .enable_reg = 0x4b008,
3151 .halt_reg = 0x24750,
3154 .enable_reg = 0x4b008,
3169 .halt_reg = 0x24884,
3172 .enable_reg = 0x4b018,
3187 .halt_reg = 0x2a018,
3190 .enable_reg = 0x4b010,
3200 .halt_reg = 0x2a00c,
3203 .enable_reg = 0x4b010,
3204 .enable_mask = BIT(0),
3213 .halt_reg = 0x2a14c,
3216 .enable_reg = 0x4b010,
3231 .halt_reg = 0x2a280,
3234 .enable_reg = 0x4b010,
3249 .halt_reg = 0x2a3b4,
3252 .enable_reg = 0x4b010,
3267 .halt_reg = 0x2a4e8,
3270 .enable_reg = 0x4b010,
3285 .halt_reg = 0x2a61c,
3288 .enable_reg = 0x4b010,
3303 .halt_reg = 0x2a750,
3306 .enable_reg = 0x4b010,
3321 .halt_reg = 0x2a884,
3324 .enable_reg = 0x4b018,
3339 .halt_reg = 0xc4018,
3342 .enable_reg = 0x4b000,
3352 .halt_reg = 0xc400c,
3355 .enable_reg = 0x4b000,
3365 .halt_reg = 0xc4280,
3368 .enable_reg = 0x4b000,
3383 .halt_reg = 0xc414c,
3386 .enable_reg = 0x4b000,
3401 .halt_reg = 0x23004,
3403 .hwcg_reg = 0x23004,
3406 .enable_reg = 0x4b008,
3416 .halt_reg = 0x23008,
3418 .hwcg_reg = 0x23008,
3421 .enable_reg = 0x4b008,
3431 .halt_reg = 0x24004,
3433 .hwcg_reg = 0x24004,
3436 .enable_reg = 0x4b008,
3446 .halt_reg = 0x24008,
3448 .hwcg_reg = 0x24008,
3451 .enable_reg = 0x4b008,
3461 .halt_reg = 0x2a004,
3463 .hwcg_reg = 0x2a004,
3466 .enable_reg = 0x4b010,
3476 .halt_reg = 0x2a008,
3478 .hwcg_reg = 0x2a008,
3481 .enable_reg = 0x4b010,
3491 .halt_reg = 0xc4004,
3493 .hwcg_reg = 0xc4004,
3496 .enable_reg = 0x4b000,
3506 .halt_reg = 0xc4008,
3508 .hwcg_reg = 0xc4008,
3511 .enable_reg = 0x4b000,
3521 .halt_reg = 0x2000c,
3524 .enable_reg = 0x2000c,
3525 .enable_mask = BIT(0),
3534 .halt_reg = 0x20004,
3537 .enable_reg = 0x20004,
3538 .enable_mask = BIT(0),
3552 .halt_reg = 0x20044,
3554 .hwcg_reg = 0x20044,
3557 .enable_reg = 0x20044,
3558 .enable_mask = BIT(0),
3572 .halt_reg = 0x9c034,
3575 .enable_reg = 0x9c034,
3576 .enable_mask = BIT(0),
3585 .halt_reg = 0x21024,
3588 .enable_reg = 0x21024,
3589 .enable_mask = BIT(0),
3598 .halt_reg = 0x21020,
3601 .enable_reg = 0x21020,
3602 .enable_mask = BIT(0),
3611 .halt_reg = 0x21004,
3614 .enable_reg = 0x21004,
3615 .enable_mask = BIT(0),
3629 .halt_reg = 0x81020,
3631 .hwcg_reg = 0x81020,
3634 .enable_reg = 0x81020,
3635 .enable_mask = BIT(0),
3644 .halt_reg = 0x81018,
3646 .hwcg_reg = 0x81018,
3649 .enable_reg = 0x81018,
3650 .enable_mask = BIT(0),
3664 .halt_reg = 0x8106c,
3666 .hwcg_reg = 0x8106c,
3669 .enable_reg = 0x8106c,
3670 .enable_mask = BIT(0),
3684 .halt_reg = 0x810a4,
3686 .hwcg_reg = 0x810a4,
3689 .enable_reg = 0x810a4,
3690 .enable_mask = BIT(0),
3704 .halt_reg = 0x81028,
3707 .enable_reg = 0x81028,
3708 .enable_mask = BIT(0),
3722 .halt_reg = 0x810c0,
3725 .enable_reg = 0x810c0,
3726 .enable_mask = BIT(0),
3740 .halt_reg = 0x81024,
3743 .enable_reg = 0x81024,
3744 .enable_mask = BIT(0),
3758 .halt_reg = 0x81064,
3760 .hwcg_reg = 0x81064,
3763 .enable_reg = 0x81064,
3764 .enable_mask = BIT(0),
3778 .halt_reg = 0x83020,
3780 .hwcg_reg = 0x83020,
3783 .enable_reg = 0x83020,
3784 .enable_mask = BIT(0),
3793 .halt_reg = 0x83018,
3795 .hwcg_reg = 0x83018,
3798 .enable_reg = 0x83018,
3799 .enable_mask = BIT(0),
3813 .halt_reg = 0x83018,
3815 .hwcg_reg = 0x83018,
3818 .enable_reg = 0x83018,
3833 .halt_reg = 0x8306c,
3835 .hwcg_reg = 0x8306c,
3838 .enable_reg = 0x8306c,
3839 .enable_mask = BIT(0),
3853 .halt_reg = 0x8306c,
3855 .hwcg_reg = 0x8306c,
3858 .enable_reg = 0x8306c,
3873 .halt_reg = 0x830a4,
3875 .hwcg_reg = 0x830a4,
3878 .enable_reg = 0x830a4,
3879 .enable_mask = BIT(0),
3893 .halt_reg = 0x830a4,
3895 .hwcg_reg = 0x830a4,
3898 .enable_reg = 0x830a4,
3913 .halt_reg = 0x83028,
3916 .enable_reg = 0x83028,
3917 .enable_mask = BIT(0),
3931 .halt_reg = 0x830c0,
3934 .enable_reg = 0x830c0,
3935 .enable_mask = BIT(0),
3949 .halt_reg = 0x83024,
3952 .enable_reg = 0x83024,
3953 .enable_mask = BIT(0),
3967 .halt_reg = 0x83064,
3969 .hwcg_reg = 0x83064,
3972 .enable_reg = 0x83064,
3973 .enable_mask = BIT(0),
3987 .halt_reg = 0x83064,
3989 .hwcg_reg = 0x83064,
3992 .enable_reg = 0x83064,
4007 .halt_reg = 0x1c018,
4010 .enable_reg = 0x1c018,
4011 .enable_mask = BIT(0),
4025 .halt_reg = 0x1c024,
4028 .enable_reg = 0x1c024,
4029 .enable_mask = BIT(0),
4043 .halt_reg = 0x1c020,
4046 .enable_reg = 0x1c020,
4047 .enable_mask = BIT(0),
4056 .halt_reg = 0x1b018,
4059 .enable_reg = 0x1b018,
4060 .enable_mask = BIT(0),
4074 .halt_reg = 0x1b024,
4077 .enable_reg = 0x1b024,
4078 .enable_mask = BIT(0),
4092 .halt_reg = 0x1b020,
4095 .enable_reg = 0x1b020,
4096 .enable_mask = BIT(0),
4105 .halt_reg = 0x2f018,
4108 .enable_reg = 0x2f018,
4109 .enable_mask = BIT(0),
4123 .halt_reg = 0x2f024,
4126 .enable_reg = 0x2f024,
4127 .enable_mask = BIT(0),
4141 .halt_reg = 0x2f020,
4144 .enable_reg = 0x2f020,
4145 .enable_mask = BIT(0),
4154 .halt_reg = 0x1b05c,
4157 .enable_reg = 0x1b05c,
4158 .enable_mask = BIT(0),
4172 .halt_reg = 0x1b060,
4175 .enable_reg = 0x1b060,
4176 .enable_mask = BIT(0),
4190 .halt_reg = 0x1b064,
4192 .hwcg_reg = 0x1b064,
4195 .enable_reg = 0x1b064,
4196 .enable_mask = BIT(0),
4210 .halt_reg = 0x2f05c,
4213 .enable_reg = 0x2f05c,
4214 .enable_mask = BIT(0),
4228 .halt_reg = 0x2f060,
4231 .enable_reg = 0x2f060,
4232 .enable_mask = BIT(0),
4246 .halt_reg = 0x2f064,
4249 .enable_reg = 0x2f064,
4250 .enable_mask = BIT(0),
4264 .halt_reg = 0x97468,
4267 .enable_reg = 0x97468,
4268 .enable_mask = BIT(0),
4277 .halt_reg = 0x34014,
4279 .hwcg_reg = 0x34014,
4282 .enable_reg = 0x34014,
4283 .enable_mask = BIT(0),
4292 .halt_reg = 0x3401c,
4294 .hwcg_reg = 0x3401c,
4297 .enable_reg = 0x3401c,
4298 .enable_mask = BIT(0),
4307 .gdscr = 0xa9004,
4308 .collapse_ctrl = 0x4b104,
4309 .collapse_mask = BIT(0),
4310 .en_rest_wait_val = 0x2,
4311 .en_few_wait_val = 0x2,
4312 .clk_dis_wait_val = 0xf,
4321 .gdscr = 0x77004,
4322 .collapse_ctrl = 0x4b104,
4324 .en_rest_wait_val = 0x2,
4325 .en_few_wait_val = 0x2,
4326 .clk_dis_wait_val = 0xf,
4335 .gdscr = 0x81004,
4336 .en_rest_wait_val = 0x2,
4337 .en_few_wait_val = 0x2,
4338 .clk_dis_wait_val = 0xf,
4347 .gdscr = 0x83004,
4348 .en_rest_wait_val = 0x2,
4349 .en_few_wait_val = 0x2,
4350 .clk_dis_wait_val = 0xf,
4359 .gdscr = 0x1c004,
4360 .en_rest_wait_val = 0x2,
4361 .en_few_wait_val = 0x2,
4362 .clk_dis_wait_val = 0xf,
4371 .gdscr = 0x1b004,
4372 .en_rest_wait_val = 0x2,
4373 .en_few_wait_val = 0x2,
4374 .clk_dis_wait_val = 0xf,
4383 .gdscr = 0x2f004,
4384 .en_rest_wait_val = 0x2,
4385 .en_few_wait_val = 0x2,
4386 .clk_dis_wait_val = 0xf,
4395 .gdscr = 0xb6004,
4396 .en_rest_wait_val = 0x2,
4397 .en_few_wait_val = 0x2,
4398 .clk_dis_wait_val = 0xf,
4407 .gdscr = 0xb4004,
4408 .en_rest_wait_val = 0x2,
4409 .en_few_wait_val = 0x2,
4410 .clk_dis_wait_val = 0xf,
4662 [GCC_CAMERA_BCR] = { 0x32000 },
4663 [GCC_DISPLAY1_BCR] = { 0xc7000 },
4664 [GCC_DISPLAY_BCR] = { 0x33000 },
4665 [GCC_EMAC0_BCR] = { 0xb6000 },
4666 [GCC_EMAC1_BCR] = { 0xb4000 },
4667 [GCC_GPU_BCR] = { 0x7d000 },
4668 [GCC_MMSS_BCR] = { 0x17000 },
4669 [GCC_PCIE_0_BCR] = { 0xa9000 },
4670 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbf000 },
4671 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbf008 },
4672 [GCC_PCIE_0_PHY_BCR] = { 0xad144 },
4673 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbf00c },
4674 [GCC_PCIE_1_BCR] = { 0x77000 },
4675 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0xae084 },
4676 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xae090 },
4677 [GCC_PCIE_1_PHY_BCR] = { 0xae08c },
4678 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 },
4679 [GCC_PDM_BCR] = { 0x3f000 },
4680 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x23000 },
4681 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x24000 },
4682 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2a000 },
4683 [GCC_QUPV3_WRAPPER_3_BCR] = { 0xc4000 },
4684 [GCC_SDCC1_BCR] = { 0x20000 },
4685 [GCC_TSCSS_BCR] = { 0x21000 },
4686 [GCC_UFS_CARD_BCR] = { 0x81000 },
4687 [GCC_UFS_PHY_BCR] = { 0x83000 },
4688 [GCC_USB20_PRIM_BCR] = { 0x1c000 },
4689 [GCC_USB2_PHY_PRIM_BCR] = { 0x5c028 },
4690 [GCC_USB2_PHY_SEC_BCR] = { 0x5c02c },
4691 [GCC_USB30_PRIM_BCR] = { 0x1b000 },
4692 [GCC_USB30_SEC_BCR] = { 0x2f000 },
4693 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x5c008 },
4694 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x5c014 },
4695 [GCC_USB3_PHY_PRIM_BCR] = { 0x5c000 },
4696 [GCC_USB3_PHY_SEC_BCR] = { 0x5c00c },
4697 [GCC_USB3_PHY_TERT_BCR] = { 0x5c030 },
4698 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x5c018 },
4699 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x5c01c },
4700 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x5c004 },
4701 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5c010 },
4702 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c020 },
4703 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c024 },
4704 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 },
4705 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x34014, 2 },
4706 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x3401c, 2 },
4707 [GCC_VIDEO_BCR] = { 0x34000 },
4751 .max_register = 0xc7018,
4791 regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); in gcc_sa8775p_probe()
4792 regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0)); in gcc_sa8775p_probe()
4793 regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0)); in gcc_sa8775p_probe()
4794 regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0)); in gcc_sa8775p_probe()
4795 regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0)); in gcc_sa8775p_probe()
4796 regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0)); in gcc_sa8775p_probe()
4797 regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0)); in gcc_sa8775p_probe()
4798 regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0)); in gcc_sa8775p_probe()
4799 regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0)); in gcc_sa8775p_probe()